Dual DLL Clock Skew Compensation for Stacked Dies
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Solution Overview
Problem
High-speed electronic systems face significant timing errors due to clock skew, which increases as clock cycles shorten, affecting system performance and accuracy in die stacking applications where clock synchronization is critical.
Innovation Solution
The apparatus employs a latch-based dual delay locked loop (DLL) technique, with one DLL module in each die, allowing for clock skew compensation without a delay measurement circuit or dummy channel, using controlled delay lines to synchronize clocks across different dies and compensate for transmission delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock cycle is reduced to increase operation speed, then productivity is improved, but clock skew becomes more significant causing timing errors
Solution Approach 1:
The patent implements a feedback mechanism where the second DLL module receives the output clock from the first DLL module and feeds it back to compensate for skew. The delay elements in both DLL modules are controlled to adjust their delay amounts based on the feedback signal, thereby compensating for transmission delays and maintaining synchronization between dies even at high operation speeds
Solution Approach 2:
The patent changes the delay parameter of the delay elements in the DLL modules to compensate for clock skew. By adjusting the delay amount dynamically, the system can maintain proper timing relationships between clocks on different dies despite the reduced clock cycle duration, thus resolving the timing accuracy issue while maintaining high productivity
2Reliability
If clock skew compensation is implemented using traditional methods with delay measurement circuits or dummy channels, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the clock skew compensation function directly into the existing DLL modules that are already present in each die for clock generation. By integrating the compensation functionality within the DLL structure itself, the patent eliminates the need for separate delay measurement circuits or dummy channels, thereby improving clock synchronization without increasing device complexity
Solution Approach 2:
The DLL modules are designed to serve multiple functions: generating the local clock signal and simultaneously compensating for clock skew from other dies. This multi-functionality approach allows the same circuit structure to perform both clock generation and skew compensation, reducing the need for additional dedicated compensation circuits and thus maintaining simplicity while achieving reliable synchronization
Data Source
AI summary
An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.