Dual DLL Clock Synchronization for Fast Frequency Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in synchronizing internal clock signals with external clock signals efficiently, particularly when the frequency changes from low to high or high to low, leading to delays and reduced operational speed.
Innovation Solution
A delay-locked-loop (DLL) circuit is designed with two DLLs, one for low-frequency and one for high-frequency external clock signals, which store locking information beforehand and generate synchronized internal clock signals using this information, allowing for rapid synchronization and increased operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single DLL circuit is used to synchronize internal clock signals with external clock signals across all frequency ranges, then the device complexity is reduced, but the synchronization time increases significantly when frequency changes occur
Solution Approach 1:
The DLL circuit is divided into two independent sub-circuits: a first DLL for low-frequency external clock signals and a second DLL for high-frequency external clock signals. Each DLL is optimized for its specific frequency range, allowing rapid synchronization without the penalties of a general-purpose single DLL. This segmentation resolves the contradiction by sacrificing some structural complexity to achieve dramatically reduced synchronization time.
2Productivity
If the DLL circuit uses a general-purpose synchronization approach for all frequency ranges, then the device structure remains simple, but the operational speed decreases during frequency transitions
Solution Approach 1:
The DLL circuit dynamically selects between the first DLL and second DLL based on the frequency range of the incoming external clock signal. A frequency detection mechanism determines which DLL is appropriate, and the system switches between them accordingly. This dynamic adaptation allows the circuit to operate at optimal speed for each frequency range while maintaining a unified overall structure.
3Loss of time
If locking information is not stored beforehand for different frequency ranges, then the device structure remains simpler, but the time required to synchronize during frequency changes increases
Solution Approach 1:
Each DLL circuit maintains pre-established locking information specific to its frequency range (low-frequency for first DLL, high-frequency for second DLL). This preliminary preparation of frequency-specific locking parameters allows the system to immediately apply the appropriate locking information when a clock signal arrives, eliminating the need to compute or establish locking parameters in real-time during frequency transitions.
Data Source
AI summary
A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.