Dual DLL Clock Jitter Feedback for Stable Signal Synchronization
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Solution Overview
Problem
Conventional clock circuits experience significant jitter due to component performance characteristics and varying operating conditions, leading to unpredictable and wide-ranging timing errors in clock signals.
Innovation Solution
A clock jitter feedback circuit is introduced, utilizing a dual delay-locked loop arrangement and a multi-signal phase detector to synchronize feedback signals, thereby reducing jitter by adjusting delays and maintaining locked conditions across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional delay-locked loop is used to generate clock signals, then the clock signal timing can be synchronized with reference clock signals, but significant jitter occurs due to component performance characteristics and varying operating conditions
Solution Approach 1:
The conventional single DLL is segmented into two separate DLLs: a first DLL that generates a first clock signal synchronized to the reference clock, and a second DLL that generates a second clock signal synchronized to the first clock signal. This segmentation allows independent optimization and jitter reduction at each stage.
Solution Approach 2:
A feedback mechanism is implemented where a feedback clock signal is generated by delaying the first clock signal through a feedback delay circuit, and a phase detector continuously monitors the phase difference between the feedback clock signal and the reference clock signal. The phase detector output adjusts the delay of the first DLL to maintain synchronization, thereby reducing jitter accumulation.
2Measurement precision
If the delay of the DLL is adjusted to synchronize clock signals, then timing synchronization is achieved, but jitter increases due to resolution limitations in delay adjustment and phase detection
Solution Approach 1:
The solution transitions from a single-dimensional delay adjustment to a two-dimensional approach by implementing a dual DLL structure with separate delay control paths. The first DLL handles coarse timing synchronization while the second DLL and feedback mechanism handle fine jitter reduction, effectively adding a temporal dimension to the delay control.
3Reliability
If a feedback path is added to reduce jitter, then timing errors are reduced, but the device complexity increases
Solution Approach 1:
The feedback delay circuit is designed to be universal, serving multiple functions: it generates the feedback clock signal for the phase detector, provides the delay path for jitter reduction, and maintains synchronization across varying operating conditions. This multi-functionality reduces the need for separate dedicated circuits for each function.
Data Source
AI summary
Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive a reference clock signal and generate an output clock signal having an adjustable phase relationship relative to the reference clock signal, and further includes a clock jitter feedback circuit coupled to a clock tree and the DLL. The clock jitter feedback circuit is configured to synchronize a clock jitter feedback signal and a DLL feedback signal that is based on the output clock signal. The clock jitter feedback circuit is further configured to provide the clock jitter feedback signal to the DLL for synchronization with a buffered reference clock signal. The clock jitter feedback signal is based on and generated in response to receiving a distributed output clock signal from the clock tree circuit and the buffered reference signal is based on the reference clock signal.