Dual Delay Locked Loops for Fast Memory Clock Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory apparatuses face challenges in achieving high data access speed due to system clock delays through clock input buffers and transmission lines, leading to synchronization issues and increased power consumption, as well as the 'stuck phenomenon' where the delay locked loop fails to adapt to voltage fluctuations.
Innovation Solution
The semiconductor memory apparatus employs two delay locked loops and a clock selection block to generate a delay locked clock by delaying the system clock and its inverse, allowing for independent phase comparisons and control of delay amounts, thereby reducing locking time and preventing the stuck phenomenon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single delay locked loop is used to compensate for clock transfer path delay, then the data access speed is improved, but the locking time becomes excessively long and the system experiences a stuck phenomenon under voltage fluctuations
Solution Approach 1:
The patent divides a single delay locked loop into two separate delay locked loops operating in parallel. Each DLL handles half of the locking process, allowing the system to achieve the required delay compensation faster than a single DLL could. This segmentation reduces the overall locking time while maintaining the ability to compensate for clock transfer path delays effectively.
Solution Approach 2:
The patent employs two delay locked loops that each perform partial delay compensation, with a clock selection block choosing the optimal output. This partial action approach allows the system to achieve the required delay compensation through multiple smaller steps rather than one large step, reducing the locking time and preventing the stuck phenomenon.
2Reliability
If the delay locked loop delays the system clock to compensate for transfer path delay, then data synchronization is improved, but power consumption increases
Solution Approach 1:
The patent segments the delay compensation function into two parallel delay locked loops, each handling a portion of the delay compensation. This allows the clock selection block to choose the most efficient output, potentially reducing overall power consumption by selecting the DLL that achieves synchronization with minimal delay adjustment.
Solution Approach 2:
The patent introduces dynamic selection between two delay locked loop outputs through the clock selection block. This dynamic approach allows the system to adapt to varying conditions and select the most power-efficient path, reducing overall power consumption while maintaining reliable data synchronization.
3Device complexity
If a single delay locked loop is used, then the device complexity is reduced, but the system cannot adapt to voltage fluctuations and experiences the stuck phenomenon
Solution Approach 1:
The patent divides the delay locked loop function into two separate loops, each capable of independent operation. This segmentation provides redundancy and adaptability, allowing the system to switch between the two DLLs based on voltage conditions, thereby preventing the stuck phenomenon while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent changes the operational parameters by using two delay locked loops with potentially different delay characteristics. This allows the system to adapt to voltage fluctuations by selecting the DLL whose parameters are most suitable for current operating conditions, improving adaptability without excessive complexity.
4Productivity
If the system uses double data rate synchronous memory access, then data access speed is improved, but the requirement for precise clock synchronization increases complexity
Solution Approach 1:
The patent segments the clock synchronization function into two parallel delay locked loops, each handling a portion of the synchronization task. This segmentation simplifies the control logic within each DLL while achieving the precise synchronization required for DDR operation, effectively managing the complexity through modular design.
Solution Approach 2:
The patent uses two delay locked loops that each perform partial synchronization, with the clock selection block choosing the optimal output. This partial action approach achieves the precise clock synchronization required for DDR memory access while distributing the complexity across multiple simpler components rather than one complex synchronization mechanism.
Data Source
AI summary
A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.