Dual Delay Locked Loop Clocking for High-Frequency Phase Alignment
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Solution Overview
Problem
Existing semiconductor apparatuses face challenges in maintaining precise phase synchronization of internal clock signals due to phase differences caused by delay time variations within the devices, particularly when using dual delay locked loops, which can lead to phase skew and inaccuracies in high-frequency operations.
Innovation Solution
The implementation of a dual delay locked loop circuit comprising a digital delay locked loop and an analog delay locked loop, with a voltage-controlled delay line, calibration circuit, phase detector, and charge pump, to perform delay-locking operations on both the reference and internal clock signals, ensuring precise phase alignment and compensation for modelled delay times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single delay locked loop is used for clock signal synchronization, then the device complexity is low, but the phase synchronization precision deteriorates at high frequencies
Solution Approach 1:
The delay locked loop is segmented into two independent loops: a first delay locked loop that performs delay-locking on a reference clock signal, and a second delay locked loop that performs delay-locking on an internal clock signal. Each loop independently compensates for phase differences in its respective signal path, thereby maintaining high phase synchronization precision without requiring a single complex unified structure.
Solution Approach 2:
Both delay locked loops share common functional blocks including the voltage-controlled delay line, phase detector, and charge pump. This multi-functional design allows the same hardware resources to serve dual purposes: the first loop handles reference clock synchronization while the second loop handles internal clock synchronization, reducing overall device complexity while maintaining precision.
2Reliability
If delay-locking operation is performed on both reference and internal clock signals, then the phase skew compensation improves, but the device complexity increases
Solution Approach 1:
The first and second delay locked loops are merged by sharing common functional blocks including the voltage-controlled delay line, phase detector, and charge pump. This consolidation allows both loops to perform delay-locking operations on their respective clocks while using shared resources, thereby improving phase skew compensation without proportionally increasing device complexity.
Solution Approach 2:
The voltage-controlled delay line serves as an intermediary component that receives control signals from both phase detectors and adjusts the phase of clock signals accordingly. This intermediary mechanism enables both delay locked loops to achieve precise phase alignment without requiring completely separate hardware paths, thus improving reliability while controlling complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables precise phase synchronization of internal clock signals across semiconductor apparatuses, effectively addressing phase skew and ensuring accurate operation even at high frequencies by utilizing both digital and analog delay locked loops to compensate for delay variations.
Implementation Method 1
The voltage-controlled delay line may delay a reference clock signal based on a delay control voltage to generate an internal clock signal and a feedback clock signal
Implementation Method 2
The phase detector configured to compare phases between the delayed reference clock signal and the delayed feedback clock signal to generate a phase detection signal
Implementation Method 3
The charge pump may generate the delay control voltage based on the phase detection signal
Data Source
AI summary
A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.