Dual Delay Locked Loop Clocking for Phase Skew Compensation
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Solution Overview
Problem
Existing semiconductor apparatuses face challenges in synchronizing internal clock signals with external clock signals due to phase differences caused by delay times within the apparatus, which can lead to phase skew issues, especially when using dual delay locked loops with process variations between delay lines.
Innovation Solution
A semiconductor apparatus incorporating a dual delay locked loop circuit with both digital and analog delay locked loops, featuring a voltage-controlled delay line, calibration circuit, phase detector, and charge pump, to perform delay-locking operations and generate internal clock signals with precise phase differences, thereby compensating for delay times and phase mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single delay locked loop is used, then the device complexity is low, but the phase alignment precision is insufficient due to process variations
Solution Approach 1:
The patent divides the delay locked loop system into two separate loops: a first delay locked loop for coarse phase adjustment and a second delay locked loop for fine phase adjustment. This segmentation allows each loop to be optimized for its specific function, improving overall phase alignment precision while managing device complexity through functional decomposition
Solution Approach 2:
The patent implements a dynamic switching mechanism where the system transitions from using the first delay locked loop during initial operation to using the second delay locked loop when phase alignment precision requirements are met. This dynamic approach allows the system to adapt its complexity based on operational needs, achieving high precision only when necessary
2Measurement precision
If dual delay locked loops are used, then the phase alignment precision is improved, but the device complexity increases
Solution Approach 1:
The patent implements a dynamic switching mechanism where the system transitions from using the first delay locked loop during initial operation to using the second delay locked loop when phase alignment precision requirements are met. This dynamic approach allows the system to adapt its complexity based on operational needs, achieving high precision only when necessary
Solution Approach 2:
The patent introduces a controller as an intermediary that manages the two delay locked loops and switches between them based on phase alignment requirements. This intermediary coordinates the operation of both loops, allowing the system to leverage the precision of the second loop only when needed while maintaining the simplicity of the first loop for routine operations
3Reliability
If delay locked loop is used, then the phase difference is compensated, but the delay time increases
Solution Approach 1:
The patent segments the phase compensation function into two stages: the first delay locked loop handles large phase differences with coarser delay steps, while the second delay locked loop handles fine phase adjustments with smaller delay steps. This segmentation allows the system to achieve precise synchronization with reduced overall delay by using the appropriate loop for the current phase error magnitude
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual delay locked loop circuit effectively synchronizes internal clock signals with external clock signals, ensuring precise phase alignment and reducing phase skew, even at high frequencies, by utilizing both digital and analog delay locked loops to compensate for delay times and process variations.
Implementation Method 1
The voltage-controlled delay line may delay a reference clock signal based on a delay control voltage to generate an internal clock signal and a feedback clock signal
Implementation Method 2
The phase detector configured to compare phases between the delayed reference clock signal and the delayed feedback clock signal to generate a phase detection signal
Implementation Method 3
The charge pump may generate the delay control voltage based on the phase detection signal
Data Source
AI summary
A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.