Dual Delay Locked Loop Clock Alignment for Phase Skew Control
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Solution Overview
Problem
Existing semiconductor apparatuses face challenges in achieving precise phase synchronization of internal clock signals due to phase differences caused by delay time variations within the devices, particularly when using dual delay locked loops, which can lead to phase skew and errors.
Innovation Solution
A semiconductor apparatus is designed with a dual delay locked loop circuit comprising a digital and an analog delay locked loop, utilizing a voltage-controlled delay line, calibration circuit, phase detector, and charge pump to perform delay-locking operations on both the reference and internal clock signals, ensuring precise phase alignment through adaptive delay control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single delay locked loop is used for clock signal synchronization, then the device complexity is low, but the phase synchronization precision is insufficient due to delay time variations
Solution Approach 1:
The patent divides the clock signal processing into two separate delay locked loops: a first DPLL for coarse phase adjustment and a second DPLL for fine phase adjustment. This segmentation allows each loop to specialize in different aspects of phase synchronization, achieving higher overall precision without requiring a single overly complex system. The first DPLL handles reference clock signals while the second handles internal clock signals, with both working together to eliminate phase skew.
Solution Approach 2:
The patent introduces a hierarchical dimension to phase synchronization by creating a two-stage DPLL system. The first DPLL operates at a higher level for coarse adjustment, while the second DPLL operates at a finer level for precise alignment. This dimensional approach to phase control enables the system to achieve high synchronization precision by addressing phase errors at multiple levels of granularity.
2Reliability
If delay time variations are compensated within the semiconductor apparatus, then the phase synchronization is improved, but additional delay locked loop circuits are required increasing device complexity
Solution Approach 1:
The patent employs dynamic phase adjustment mechanisms within each DPLL to continuously compensate for delay time variations. The first DPLL dynamically adjusts the phase of the reference clock signal, while the second DPLL dynamically adjusts the phase of the internal clock signal. This dynamic adaptation allows the system to maintain reliable phase synchronization under varying operating conditions without requiring excessive circuit complexity.
Solution Approach 2:
Each delay locked loop incorporates feedback mechanisms that monitor phase differences and automatically adjust delay elements to eliminate phase skew. The first DPLL uses feedback from phase comparison of reference clock signals, while the second DPLL uses feedback from phase comparison of internal clock signals. This feedback control enables reliable phase compensation while keeping the added circuit complexity manageable through efficient control logic.
3Productivity
If high frequency clock signals are transmitted, then the productivity is improved, but phase skew and synchronization errors increase
Solution Approach 1:
The patent performs preliminary phase adjustment in the first DPLL before the clock signals are transmitted and processed further. By pre-compensating phase differences in the reference clock signal path, the system reduces the burden on subsequent timing circuits and maintains better synchronization accuracy even at high frequencies. This preliminary action prevents phase skew from accumulating during high-speed operation.
Solution Approach 2:
The dual DPLL system provides dynamic phase correction that adapts to high-frequency operation. The first DPLL dynamically adjusts reference clock phase while the second DPLL dynamically adjusts internal clock phase, allowing the system to maintain precise synchronization even as clock frequencies increase. This dynamic response enables the system to handle high-speed data transmission without suffering from increased phase skew.
Data Source
AI summary
A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.