Dual DPLL Unmodulation Coupling for Low-Jitter Clock Synchronization
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Solution Overview
Problem
Existing timing circuits with multiple analog and digital phase-locked loops face challenges in reducing jitter due to the size and inductive coupling issues of analog phase-locked loops, and bandwidth restrictions in implementations with fractional output dividers.
Innovation Solution
A semiconductor device incorporating a combination of analog and digital phase-lock loops, where a first DPLL controls an APLL, and a second DPLL is coupled to a fractional output divider, allowing for unmodulation coupling by subtracting the modulation signal from the first DPLL, thereby suppressing modulation regardless of bandwidth differences between the loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple analog phase-locked loops are used to synchronize networks, then timing synchronization capability is improved, but device size and inductive coupling issues increase
Solution Approach 1:
The patent replaces analog phase-locked loops with digital phase-locked loops to eliminate inductive coupling issues and reduce device size. The digital PLL uses digital signal processing instead of analog components, substituting the mechanical/electrical analog system with a digital system that achieves the same timing synchronization function without the physical coupling problems.
Solution Approach 2:
The patent changes the bandwidth parameters of the digital PLLs to be similar rather than widely different, which optimizes the unmodulation coupling effect. By adjusting the bandwidth parameter to be comparable across multiple DPLLs, the system achieves better jitter reduction while maintaining independent operation of each loop.
2Adaptability or versatility
If fractional output dividers are used in DPLL implementations, then frequency division capability is improved, but bandwidth restrictions are imposed
Solution Approach 1:
The patent applies partial unmodulation coupling by subtracting only the modulation signal portion from the first DPLL from the second DPLL output, rather than completely isolating the loops. This partial action allows the fractional output dividers to maintain their frequency division capability while removing the harmful modulation coupling, achieving the desired effect without excessive complexity.
3Speed
If modulation signals are coupled between DPLLs, then frequency control is improved, but jitter increases
Solution Approach 1:
The patent extracts and removes the modulation signal from the first DPLL by subtracting it from the second DPLL output. This extraction isolates the harmful modulation component that causes jitter, allowing the frequency control functionality to be maintained through the fractional output dividers while eliminating the jitter-inducing coupling effect.
Data Source
AI summary
Semiconductor devices for synchronizing networks are described. A semiconductor device can include an analog phase-lock loop (APLL) configured to output a first signal. The semiconductor device can further include a first digital phase-lock loop (DPLL) configured to output a second signal. The semiconductor device can further include a second DPLL configured to output a third signal. A combination of the first signal and the second signal can be used to generate a first output clock signal. A difference resulting from a subtraction of the second signal from the third signal can be used to generate a second output clock signal.