Dual ECC Encoding for Multi-Bit Error Detection in Data Processing
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Solution Overview
Problem
Existing ECC-based data error detection methods fail to effectively detect even-numbered bit errors and can erroneously correct odd-numbered bit errors, leading to inefficiencies in error detection and correction processes.
Innovation Solution
A data processing device that employs two ECC encoder units with different ECC generation matrices to generate and use dual ECCs for error detection, where one ECC is generated by permuting the bits of the input data and the other by permuting the columns of the ECC generation matrix, enhancing error detection performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single ECC is used for error detection, then the device complexity is low, but the error detection performance is insufficient for even-numbered bit errors and odd-numbered bit errors
Solution Approach 1:
The patent divides the error detection function into two separate ECC systems: a first ECC for normal error detection and a second ECC specifically for detecting uncorrectable errors (such as even-numbered bit errors and odd-numbered bit errors). This segmentation allows each ECC to specialize in detecting specific error types, thereby improving overall error detection performance without requiring a complete redesign of the entire error detection system
Solution Approach 2:
The patent introduces a second dimension of error detection by adding the second ECC system that operates independently from the first ECC. This second ECC provides an additional detection layer that complements the first ECC, enabling the system to detect error types that the first ECC alone cannot detect, thus enhancing reliability through dimensional expansion
2Reliability
If counter circuit is added to count the number of 1s in data, then the error detection rate for multiple bits is improved, but the write and read time to memory increases
Solution Approach 1:
The patent replaces the mechanical counting approach (using counter circuits to count the number of 1s in data) with an algebraic approach using the second ECC system. The second ECC is generated through algebraic operations on the data bits, which can be performed more efficiently in parallel without requiring sequential counting operations, thereby reducing the time overhead for error detection
3Productivity
If the clock frequency is raised to reduce processing time, then the error detection speed is improved, but the power consumption and system complexity increase
Solution Approach 1:
The patent employs dynamic error detection strategies where the second ECC is generated and used conditionally based on the detection needs. The system dynamically switches between using only the first ECC for normal operations and engaging the second ECC when enhanced detection is required, thereby optimizing the balance between error detection speed and power consumption without requiring continuous high-frequency operation
Data Source
AI summary
The subject is to improve the detection performance in the error detection of data using an ECC. A data processing device 1 includes an encoder device 2 that includes an encoder unit to generate an ECC by performing operations according to a first ECC generation matrix and an encoder unit 5 to generate an ECC by performing operations according to a second ECC generation matrix obtained by permutating a column of the first ECC generation matrix. The encoder unit 4 generates the first ECC for the first data. The encoder unit 5 generates the second ECC for the second data obtained by permutating a bit of the first data.