Dual ECC Flash Memory Control for Multi-Bit Read Accuracy
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Solution Overview
Problem
Flash memory devices face increasing errors due to overlapping threshold voltage distributions as the number of data bits stored in a cell increases, leading to read errors exacerbated by factors like charge loss, time elapse, temperature changes, and cell defects.
Innovation Solution
A dual ECC (error correction code) system is implemented, comprising a first ECC block using linear block coding and a second ECC block using maximum likelihood methods, to generate and store ECC data, enhancing error detection and correction capabilities in multi-bit data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of data bits stored in a memory cell is increased, then the storage capacity is improved, but the read accuracy deteriorates due to overlapping threshold voltage distributions
Solution Approach 1:
The patent divides the error correction process into two independent stages: first ECC block handles initial error correction, and second ECC block performs additional error correction on the output of the first block. This segmentation allows each ECC block to focus on correcting specific types of errors, thereby improving overall read accuracy while maintaining multi-bit storage capacity.
Solution Approach 2:
The patent transitions from a single-level error correction approach to a two-level hierarchical error correction system. By adding the dimension of multiple correction stages with different correction capabilities, the system can handle the increased error rates associated with multi-bit storage without sacrificing storage density.
2Device complexity
If a single ECC block is used for error correction, then the device complexity is low, but the error correction capability is insufficient for multi-bit data
Solution Approach 1:
The patent segments the error correction function into two distinct blocks: the first ECC block performs initial error correction, and the second ECC block provides additional correction for residual errors. This segmentation enables the system to achieve high reliability for multi-bit data while keeping each individual ECC block relatively simple in structure.
Solution Approach 2:
The patent implements a nested error correction structure where the second ECC block operates on the output of the first ECC block. This nested arrangement allows the system to layer correction capabilities, with the outer correction layer addressing errors that penetrate the inner correction layer, thereby achieving high reliability without requiring a single overly complex ECC structure.
3Quantity of substance
If multiple threshold voltage distributions are used for multi-bit storage, then the storage density is improved, but the overlap between distributions increases causing more read errors
Solution Approach 1:
The patent applies preliminary error correction in the first ECC block before data is read from the memory cell. This preliminary action corrects errors that arise from threshold voltage distribution overlap, thereby reducing the number of read errors that reach the output stage and improving overall system reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the output of the first ECC block is fed into the second ECC block for additional correction. This feedback loop allows the system to identify and correct errors that were not caught by the first correction stage, thereby compensating for the increased error rates caused by using multiple threshold voltage distributions for high-density storage.
Data Source
AI summary
An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.