Dual ECC Flash Memory Control for Multi-Bit Read Errors
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Solution Overview
Problem
Multi-bit data storage in flash memory devices is prone to errors due to overlapping threshold voltage distributions, which increases as the number of data bits stored in one memory cell increases, leading to read errors and data corruption.
Innovation Solution
A dual ECC (error correction code) controller system that employs a first ECC block using linear block coding and a second ECC block using maximum likelihood encoding to generate and store ECC data, ensuring accurate data reading and correction in flash memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is stored in one memory cell to increase storage capacity, then storage density is improved, but read error rate increases due to overlapping threshold voltage distributions
Solution Approach 1:
The patent divides the error correction function into two separate ECC blocks: a first ECC block that processes program data to generate first ECC data, and a second ECC block that processes both the first ECC data and program data to generate second ECC data. This segmentation allows each ECC block to specialize in different error correction tasks, with the first block handling basic error correction and the second block handling more complex error patterns, thereby improving overall reliability while maintaining multi-bit storage capacity.
Solution Approach 2:
The patent employs a composite error correction approach by combining two different ECC schemes in sequence. The first ECC block applies one type of error correction code to the program data, and the second ECC block applies a different error correction code to the combined first ECC data and program data. This composite approach leverages the strengths of both ECC schemes to achieve better error correction performance than either scheme alone, effectively addressing the increased error rates from multi-bit storage.
2Quantity of substance
If more threshold voltage distributions are used to read multi-bit data, then data storage capability is improved, but threshold voltage overlap increases causing more errors
Solution Approach 1:
The patent introduces an additional dimension of error correction by implementing a two-level ECC structure. Instead of relying solely on threshold voltage separation in the traditional dimension, the system adds another layer of protection through sequential ECC processing. The first ECC block provides initial error correction, and the second ECC block provides additional correction for the combined data and first ECC data, effectively adding a dimensional layer of error mitigation that compensates for the reduced threshold voltage separation precision required for multi-bit storage.
3Device complexity
If a single ECC scheme is used for error correction, then device complexity is kept low, but error correction effectiveness is insufficient for multi-bit data
Solution Approach 1:
The patent segments the error correction functionality into two distinct ECC blocks with different processing roles. The first ECC block is dedicated to processing program data and generating first ECC data, while the second ECC block processes both the first ECC data and program data to generate second ECC data. This segmentation allows each block to be optimized for its specific function, improving overall error correction effectiveness while keeping each individual block relatively simple in structure.
Solution Approach 2:
The second ECC block serves multiple functions: it processes the program data again, incorporates the first ECC data generated by the first block, and generates the final second ECC data. This multi-functional approach allows the system to achieve enhanced error correction capability without proportionally increasing the number of separate components, as the second ECC block handles multiple correction tasks in sequence.
Data Source
AI summary
An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.