Dual-Scheme ECC Control for Multi-Bit Flash Read Reliability
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Solution Overview
Problem
Flash memory devices face increased error rates due to overlapping threshold voltage distributions as the number of bits stored per cell increases, leading to unreliable data read operations.
Innovation Solution
Implementing an ECC controller with dual error correction schemes, using a high-speed BCH code for fewer errors and a high-performance RS code for more errors, to selectively correct errors in read data based on the number of errors detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is stored per cell to increase storage capacity, then storage density is improved, but error rate increases due to overlapping threshold voltage distributions
Solution Approach 1:
The patent segments the error correction task into two distinct parts: a first ECC scheme (e.g., BCH code) for correcting a limited number of errors quickly, and a second ECC scheme (e.g., RS code) for correcting more errors with higher performance. This segmentation allows the system to handle different error scenarios with appropriate methods, resolving the contradiction between storage capacity and reliability by providing targeted error correction for multi-bit per cell storage.
Solution Approach 2:
The patent changes the parameter of error correction capability by selecting between different ECC schemes based on the number of errors detected. The system dynamically adjusts the error correction strength - using lighter correction for fewer errors and stronger correction for more errors - thereby maintaining data reliability across varying storage densities and error conditions.
2Reliability
If a single high-performance ECC scheme is used to correct all errors, then data reliability is improved, but processing time increases
Solution Approach 1:
The patent implements a dynamic error correction system that adapts its approach based on the actual error conditions. The decoder first attempts correction with the faster first ECC scheme, and only if that fails does it proceed to the more time-consuming second ECC scheme. This dynamic adaptation resolves the contradiction by optimizing processing time for typical cases while maintaining reliability for severe error cases.
Solution Approach 2:
The patent applies partial error correction by using the first ECC scheme to handle the majority of error cases that require less intensive correction. The second ECC scheme is reserved for exceptional cases with more errors. This partial application of full error correction capability reduces average processing time while maintaining overall data integrity.
3Reliability
If dual ECC schemes are implemented to handle different error scenarios, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by having the first ECC scheme attempt error correction before the second ECC scheme is engaged. This preliminary attempt with the simpler, faster code handles most cases, and only when it fails does the system proceed to the more complex second scheme. This preliminary filtering approach improves error correction capability while managing device complexity through hierarchical processing.
Solution Approach 2:
The patent uses the first ECC scheme as an intermediary between the raw data and the second ECC scheme. This intermediary layer handles the bulk of error correction tasks, filtering out cases that require the more complex second scheme. This intermediary approach enhances overall error correction capability while keeping the system architecture manageable through staged processing.
Data Source
AI summary
An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.