Dual ECC Memory Controller Latency Reduction
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Solution Overview
Problem
The increasing capacity of memory devices has made it difficult to fabricate memory devices with no defective cells, leading to the need for error correction methods such as redundancy memory cells and error correction circuits, which result in significant latency during data transmission and processing.
Innovation Solution
A memory system and integrated circuit system that utilize a first error correction code for initial error detection and correction, followed by a second error correction code with enhanced error correction ability, reducing latency by parallelizing operations and optimizing error correction processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuits and redundancy memory cells are used to correct errors in high-capacity memory devices, then reliability is improved, but latency is increased
Solution Approach 1:
The patent performs preliminary error correction during the write operation before data is stored in the memory device. The error correction circuit corrects errors in the write data and generates corrected write data in advance, so that when data is subsequently read, the correction has already been completed, reducing the latency experienced during read operations.
Solution Approach 2:
The patent segments the error correction process into distinct stages: initial error detection using first ECC, conditional error correction using the first error correction circuit, and secondary ECC generation. This segmentation allows different correction operations to be performed based on error conditions, optimizing the balance between reliability and latency.
2Reliability
If comprehensive error correction is performed on all data, then reliability is improved, but productivity is reduced due to increased processing time
Solution Approach 1:
The patent applies partial error correction by using the first error correction circuit only when errors are detected through the first ECC. For error-free data, the system proceeds directly to generating second ECC without performing full error correction, thus maintaining high productivity while ensuring reliability when needed.
Solution Approach 2:
The patent changes the error correction parameter dynamically based on error detection results. When errors are detected, comprehensive error correction is applied; when no errors are detected, a simplified process is used. This parameter change optimizes the balance between reliability and productivity.
Data Source
AI summary
A memory system may include a memory controller suitable for transmitting write data and a first write ECC corresponding to the write data during a write operation, a first error correction circuit suitable for detecting whether the write data received from the memory controller has an error, using the first write ECC received from the memory controller, and correcting the error when the error is detected, a second ECC generation circuit suitable for generating a second write ECC using the write data received from the memory controller, and generating the second write ECC using the write data whose error has been corrected by the first error correction circuit, when the detection of the error is noticed from the first error correction circuit, and one or more memories suitable for storing the second write ECC and write data corresponding to the second write ECC.