Dual-ECC Memory Operation for Adaptive Error Correction
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Solution Overview
Problem
As memory capacity increases, it becomes challenging to manufacture memory systems with no failed memory cells, leading to the need for error correction mechanisms such as redundancy and error correction circuits to address errors during read and write processes.
Innovation Solution
A memory system that employs a dual error correction mode using different error correction codes (ECC_L and ECC_S) and parity generation circuits to improve error correction efficiency, with ECC_L providing high error correction capability in the first mode and ECC_S in the second mode, allowing for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single error correction code is used for all memory operations, then the error correction capability is uniform, but the error correction efficiency is reduced due to unnecessary computation in low-error scenarios
Solution Approach 1:
The patent implements dynamic error correction by switching between two different error correction codes (first ECC and second ECC) based on the error characteristics of the data. The system determines whether to apply the first error correction code or the second error correction code according to the error situation, making the error correction process adaptive rather than static. This dynamic approach allows the system to use the more powerful first ECC only when necessary, while using the lighter second ECC for normal operations, thereby improving overall efficiency.
Solution Approach 2:
The patent changes the parameters of error correction by using two different error correction codes with different correction capabilities and computational complexities. The first error correction code has stronger correction capability for handling high-bit error scenarios, while the second error correction code has lower computational complexity for low-bit error scenarios. By selecting appropriate error correction parameters based on the error situation, the system optimizes the balance between reliability and efficiency.
2Reliability
If a powerful error correction code is always used, then error correction capability is maximized, but computational complexity and processing time increase
Solution Approach 1:
The patent applies partial error correction action by using the powerful first error correction code only when errors are detected, rather than always applying it. For error-free or low-error data, the system uses the simpler second error correction code or no correction at all. This partial application of the more complex error correction mechanism reduces unnecessary computational complexity while maintaining adequate error correction capability when needed.
Solution Approach 2:
The patent segments the error correction process into two distinct paths: one using the first error correction code for high-error scenarios and another using the second error correction code for low-error scenarios. This segmentation allows the system to handle different error conditions with appropriately matched correction mechanisms, avoiding the unnecessary application of complex correction algorithms to simple cases.
3Reliability
If error correction is performed on all data, then all errors are corrected, but processing speed is reduced due to additional computation
Solution Approach 1:
The patent implements dynamic error correction processing by determining whether error correction is necessary before performing it. The system checks for errors and then selectively applies either the first or second error correction code based on the error situation. For data without errors or with minor errors, the correction process is simplified or skipped, thereby maintaining processing speed while ensuring error correction completeness when needed.
Solution Approach 2:
The patent performs preliminary error detection before applying error correction. By checking for errors first and then applying correction only when necessary, the system prevents unnecessary computation on error-free data. This preliminary anti-action approach maintains processing speed by avoiding redundant correction operations while ensuring that actual errors are corrected.
Data Source
AI summary
A memory system may include an error correction code generation circuit configured to generate a first error correction code having a large bit number by using write data and a first H matrix in a first error correction mode, and to generate a second error correction code having a small bit number by using the write data and a second H matrix in a second error correction mode, and a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode.