Dual-Scheme ECC Controller for MLC Flash Read Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices face increased error rates due to overlapping threshold voltage distributions as the number of bits stored per cell increases, leading to unreliable data read operations.
Innovation Solution
Implementing an ECC controller with dual error correction schemes, using a high-speed BCH code for fewer errors and a high-performance RS code for more errors, to selectively correct errors based on the number of errors detected in read data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored per cell increases in MLC flash memory devices, then storage capacity increases, but error rate increases due to overlapping threshold voltage distributions
Solution Approach 1:
The patent divides the error correction task into two separate schemes: a first error correction scheme for correcting a first number of errors and a second error correction scheme for correcting a second number of errors. This segmentation allows the system to handle different error scenarios with optimized approaches, improving overall reliability while maintaining high storage capacity in MLC flash memory devices
Solution Approach 2:
The patent changes the parameter of error correction capability by implementing multiple error correction schemes with different correction capacities. The system selectively applies the appropriate scheme based on the detected error count, thereby adapting to varying reliability requirements while preserving the high-density storage structure
2Reliability
If a single high-performance error correction scheme is used to correct all errors, then reliability improves, but processing time increases
Solution Approach 1:
The patent implements a dynamic error correction approach where the system first detects the number of errors and then selectively applies either a first error correction scheme or a second error correction scheme. This dynamic selection optimizes processing time by using the appropriate correction level for each error scenario, rather than always applying the most comprehensive correction
Solution Approach 2:
The patent applies partial error correction by using a first error correction scheme for smaller error counts and a second error correction scheme for larger error counts. This partial action approach avoids the excessive processing time that would result from always applying the most comprehensive correction scheme, while still achieving sufficient reliability for each case
Data Source
AI summary
An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors.