Dual ECC Decoding for Solid-State Storage Bit Error Correction

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Solution Overview

Problem

Solid-state storage devices experience bit errors due to increasing bit densities and changes in manufacturing and use conditions, making them incompatible with existing drivers or software over time, and requiring effective error correction mechanisms.

Innovation Solution

A system and method that utilize both hardware and software error-correcting code (ECC) decoders to validate and correct data errors, with the hardware ECC decoder handling errors during runtime and the software ECC decoder extending data retention by correcting additional errors, using a flexible error protection management policy that adapts to changing error rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If bit density of solid-state memory media is increased, then storage capacity is improved, but the number of bit errors increases

Engineering Contradiction:
Improvestorage capacityVSAvoidbit error rate
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The error correction functionality is segmented into two independent decoders: a hardware ECC decoder for fast runtime correction and a software ECC decoder for comprehensive retention correction. This segmentation allows each decoder to be optimized for its specific function while working together to handle the increased bit errors from high-density media.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system uses a composite error correction approach combining hardware and software decoding mechanisms. The hardware decoder provides quick correction for common errors during runtime, while the software decoder handles more complex error patterns that occur during data retention, creating a layered defense against bit errors.

Inventive Principle:
Principle #40Composite materials

2Speed

If hardware ECC decoder is used for runtime error correction, then correction speed is improved, but the number of correctable errors is limited

Engineering Contradiction:
Improvecorrection speedVSAvoiderror correction capability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system introduces a software ECC decoder as an intermediary that handles error correction cases beyond the hardware decoder's capabilities. The hardware decoder processes errors within its threshold during runtime, and the software decoder acts as a backup for more severe errors, ensuring comprehensive protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The hardware decoder performs partial error correction for errors within its correction threshold during runtime operations. The software decoder provides excessive correction capability for errors exceeding the hardware threshold, ensuring that even severe errors can be corrected when they occur during data retention.

Inventive Principle:
Principle #16Partial or excessive action

3Duration of action of stationary object

If software ECC decoder is used to extend data retention, then data retention time is improved, but processing overhead increases

Engineering Contradiction:
Improvedata retention timeVSAvoidprocessing overhead
Core Design Contradiction:
Duration of action of stationary objectVSUse of energy by moving object

Solution Approach 1:

The software ECC decoder is activated only partially - specifically when errors exceed the hardware decoder's correction threshold during runtime or when validating data after retention period. This partial activation minimizes processing overhead while still providing extended retention capability when needed.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The dual-decoder system serves itself by having the hardware decoder handle routine runtime errors automatically, eliminating the need for software decoder intervention during normal operations. The software decoder only activates when the hardware decoder indicates it cannot correct the errors, optimizing energy usage.

Inventive Principle:
Principle #25Self-service

4Reliability

If error correction capability is increased to handle aging effects, then data reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoiddecoder architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error correction system is segmented into hardware and software components with clearly defined responsibilities. The hardware decoder handles fast runtime correction for common errors, while the software decoder handles comprehensive validation for retention errors. This segmentation manages complexity by dividing functions into manageable, independent modules.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The software ECC decoder serves multiple functions: it validates data after runtime operations, corrects errors that exceed hardware capabilities, and extends data retention validation. This multi-functionality justifies the added complexity by providing comprehensive error protection across different operational phases.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8892980B2Apparatus, system, and method for providing error correction
Publication Date: 2014.11.18 SANDISK TECHNOLOGIES LLC
  • US8892980B2 patent drawing
  • US8892980B2 patent drawing
  • US8892980B2 patent drawing

AI summary

An apparatus, system, and method are disclosed for providing error correction for a data storage device. A determination module determines an error-correcting code (“ECC”) characteristic of the data storage device. An ECC module validates requested data read from the data storage device using a hardware ECC decoder. In response to the requested data satisfying a correction threshold, a software ECC decoder module validates the data using a software ECC decoder. The software ECC decoder is configured according to the ECC characteristic of the data storage device.