Dual Eclipse Circuit for CMOS Image Sensor Shading
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Solution Overview
Problem
CMOS image sensors face challenges with vertical shading due to increased column bus resistance and pixel array miniaturization, which affects image quality, especially in large pixel arrays and backside illumination technology, where light absorption is insufficient, leading to issues like oversaturation and spatial distortion.
Innovation Solution
The implementation of anti-eclipse voltage clamp circuits at both the top and bottom of each column line, coupled with two rows of anti-eclipse circuits, helps to rapidly settle the clamp voltage and reduce vertical shading, allowing for high frame rates and improved image quality without the need for full readout circuits at each column.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel arrays are miniaturized to increase resolution, then the number of pixels increases, but column bus resistance increases causing vertical shading
Solution Approach 1:
The anti-eclipse circuit is segmented into two independent voltage clamp circuits positioned at opposite ends (top and bottom) of the pixel array. Each clamp circuit independently controls the voltage at its respective end of the column bus, effectively dividing the single long column bus into two shorter electrical paths. This segmentation reduces the overall resistance impact and eliminates vertical shading caused by the long column bus in miniaturized high-resolution sensors.
2Measurement precision
If pixel size is decreased to increase array density, then more pixels fit in the sensor, but light absorption depth becomes insufficient especially for long-wavelength light
Solution Approach 1:
The patent employs backside illumination (BSI) technology, which inverts the traditional front-illuminated sensor architecture. By illuminating the sensor from the backside, light enters the photodiode region directly without passing through metal interconnect layers and other obstructive structures. This dimensional change in light incidence allows smaller pixels to maintain sufficient light absorption depth, particularly for long-wavelength red light, while achieving higher pixel array density.
3Device complexity
If rolling shutter mode is used to simplify readout, then circuit complexity is reduced, but spatial distortion occurs in fast-moving objects
Solution Approach 1:
The pixel array design incorporates a global shutter mechanism that allows simultaneous exposure of all pixels while maintaining the ability to read out in different sequences. The floating diffusion nodes and transfer gates are designed to support both rolling shutter readout (for lower complexity applications) and global shutter readout (for high geometric accuracy requirements). This multi-functional design enables the same sensor to adapt to different application needs without requiring separate hardware systems.
4Manufacturing precision
If anti-eclipse voltage clamp circuits are added to reduce vertical shading, then image quality improves, but device complexity increases
Solution Approach 1:
The anti-eclipse voltage clamp circuits are merged with the existing column bus structure and pixel readout circuitry. The voltage clamp circuits share common power supply lines and control signals with other sensor components, and their transistors are integrated into the standard CMOS fabrication process. This merging approach adds the necessary voltage clamping functionality to eliminate vertical shading while minimizing the increase in overall device complexity through shared infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution minimizes vertical shading and enables large pixel arrays to capture both bright and dark areas effectively, maintaining high image quality and reducing settling time, thus addressing the limitations of prior art in image sensor design.
Implementation Method 1
each pixel comprising a photodiode and pixel support circuitry
Implementation Method 2
an anti-eclipse voltage clamp circuit at both the top and bottom of each column line
Data Source
AI summary
A pixel cell and readout circuit includes an anti-eclipse voltage clamp circuit at both the top and bottom of each column line of an array of the pixel cells. The anti-eclipse voltage clamp circuits form a row with each column in the array coupled to an anti-eclipse voltage clamp circuit. The combination of two rows of anti-eclipse voltage clamp circuits helps settle the clamp voltage more rapidly and to compensate for the increased length of the anti-eclipse voltage circuit row as well as the column line resistance due to narrow metal lines and increased numbers of pixels as well as the requirement to operate a sensor at a higher frame rate. More significantly this circuit construction can minimize vertical shading in the resulting image.