Dual-Edge Sampling CDR Circuit for Fast Clock Recovery
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Solution Overview
Problem
Existing clock and data recovery (CDR) circuits face challenges such as the need for dedicated phase lock loops, high complexity in oversampling, bandwidth limitations due to feedback loops, large area occupation, significant power consumption, and lengthy lock acquisition times for the recovered clock.
Innovation Solution
A CDR circuit that includes first and second sampling circuits to take phase offset samples of a received serial data stream in response to opposite edges of a sampling clock, comparator circuits to determine the logic state of these samples, a selection circuit to choose the correct samples, and a serial to parallel converter to generate an output word.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated phase lock loop (PLL) circuit is used for clock and data recovery, then the recovery accuracy is improved, but the device complexity and area occupation increase
Solution Approach 1:
The patent extracts the essential function of phase detection from the complex PLL circuit and implements it through a simplified sampling-based phase error detector. By taking multiple samples at different phases and comparing them, the circuit achieves phase detection without requiring the full PLL infrastructure, thereby reducing complexity while maintaining recovery accuracy.
Solution Approach 2:
The patent uses multiple copies of the sampling circuit operating in parallel at different phases. Instead of using a single complex PLL, multiple simplified sampling circuits capture the data stream simultaneously at different clock phases, and their outputs are combined to achieve accurate clock and data recovery with reduced individual circuit complexity.
2Measurement precision
If oversampling technique is implemented to improve sampling accuracy, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent segments the oversampling process into multiple independent sampling operations performed in parallel. Instead of implementing a single complex oversampling circuit, the system divides the task into multiple simpler sampling circuits that operate simultaneously at different phases, each performing basic sampling without requiring complex oversampling logic.
Solution Approach 2:
The patent merges the outputs of multiple simple sampling circuits to achieve the effect of oversampling. By combining samples taken at different phases through logical operations, the system achieves high sampling accuracy without requiring each individual circuit to be complex, thus reducing overall device complexity while maintaining precision.
3Stability of the object's composition
If a feedback loop is used for clock recovery, then the lock stability is improved, but the bandwidth limitation increases
Solution Approach 1:
The patent performs preliminary phase detection by taking multiple samples at different phases before final data recovery. This preliminary sampling action allows the circuit to determine the optimal sampling phase in advance, enabling fast acquisition without requiring a slow feedback loop to adjust the clock phase continuously, thus maintaining both stability and bandwidth.
Solution Approach 2:
The sampling circuit uses its own multiple phase samples to automatically determine the correct sampling phase without external feedback. By comparing its own samples taken at different phases, the circuit self-adjusts to the optimal sampling point, eliminating the need for a bandwidth-limiting feedback loop while maintaining lock stability.
4Reliability
If traditional CDR circuitry is used, then the clock recovery function is achieved, but the power consumption increases
Solution Approach 1:
The patent uses multiple simple, low-power sampling circuits that operate in parallel rather than a single complex high-power PLL circuit. Each sampling circuit is designed to be energy-efficient and can be easily reset, allowing the system to achieve reliable clock recovery through multiple low-power operations instead of one high-power continuous operation.
Solution Approach 2:
The patent employs periodic sampling at multiple phases rather than continuous high-power operation. By taking samples at specific periodic intervals at different clock phases and selecting the optimal phase, the circuit achieves reliable clock recovery while consuming power only during sampling moments, significantly reducing average power consumption compared to continuous traditional CDR operation.
Data Source
Figure 1A
Figure 1B
Figure 1C~3A
AI summary
A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.