Data Transmission Using Dual Edge Clock Extraction

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Solution Overview

Problem

In systems with multiple synchronous devices, reliable data transmission is challenging due to clock drift and disturbances on transmission lines, leading to phase shifts and incorrect data reading, which can result in reduced bandwidth and repeated message transmissions.

Innovation Solution

The method generates two clocks from an initial clock, one from rising edges and another from falling edges, with frequencies defined as F1U = F1D = F0 ± (F0/2), allowing for reliable data reading using consecutive clock edges and error correction codes, eliminating the need for a dedicated clock line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated clock line is used to synchronize data transmission, then data transmission reliability is improved, but system complexity and cabling requirements increase

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the clock signal and data signal into a single transmission line by encoding synchronization information within the data stream itself. The receiver extracts timing information from the transmitted data sequence, eliminating the need for a separate dedicated clock line while maintaining synchronization reliability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single transmission line serves dual functions: transmitting both data and clock synchronization signals. This multi-functional approach replaces the traditional separate channels, reducing cabling complexity while preserving reliable data transmission.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If equipment uses independent clocks without synchronization, then device complexity is reduced, but clock drift causes phase shifts and reading errors

Engineering Contradiction:
Improvedevice complexityVSAvoiddata reading accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The receiver uses the transmitted data sequence itself as a reference to generate timing signals back for synchronization. By analyzing the received data pattern and extracting clock information, the system creates a feedback mechanism that compensates for independent clock drift without requiring complex external synchronization hardware.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes the frequency and phase parameters of the received signal dynamically to match the transmitter's clock characteristics. By adjusting the local clock frequency to align with the incoming data stream, the receiver compensates for frequency deviations and maintains accurate data sampling despite independent clock operation.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If transmission line disturbances are handled by retransmission, then data reliability is maintained, but useful bandwidth is reduced

Engineering Contradiction:
Improvedata reliabilityVSAvoiduseful bandwidth
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary error detection and correction by embedding redundancy and synchronization information within the original data stream before transmission. This preliminary preparation allows the receiver to identify and correct errors locally without requiring retransmission, preserving bandwidth while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3648382B1Method and system for reliable data transmission
Publication Date: 2022.03.30 THALES SA
  • EP3648382B1 patent drawingFigure 1A~2
  • EP3648382B1 patent drawingFigure 3~4
  • EP3648382B1 patent drawing

AI summary

Method and device for reliably transmitting data to at least one piece of equipment (23) wherein: From its initial clock H1, a piece of equipment (23) generates at least one first clock H1U from a rising edge of the initial clock H1 with a frequency F1U and a second clock H1D from a falling edge of the initial clock H1, with a frequency F1D. The equipment: Reads the received data using at least one first rising edge of H1U and a consecutive falling edge of the first rising edge of H1U, then reads the received data using a first rising edge of H1D and a consecutive falling edge of the first rising edge of H1D, the four clock edges used being consecutive by 2F1. Decodes at least the four messages using an error-correcting code. When at least one decoded message is correct, it uses the information contained in that message to drive a device connected to said equipment.