Dual-Edge Clock Divider for Higher Output Frequency Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Single-edge aware clock dividers are limited in frequency scaling ratio, restricting the maximum frequency of the output clock, which may not meet the requirements of cores capable of operating at higher frequencies, leading to inadequate clock provision for such cores.
Innovation Solution
A dual-edge aware clock divider that responds to both rising and falling edges of the input clock, allowing for a higher frequency scaling ratio and enabling the output clock to reach frequencies equal to the input clock, thereby supporting cores that require higher operational frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single-edge aware clock divider is used, then the device complexity is reduced, but the frequency scaling ratio is limited and the maximum output clock frequency is restricted
Solution Approach 1:
The clock divider dynamically switches between single-edge and dual-edge awareness modes based on the required frequency scaling ratio. The circuit can adapt its operation mode to match the operational requirements of different cores, enabling it to achieve higher frequency scaling ratios when needed while maintaining simpler operation for lower frequency requirements.
Solution Approach 2:
The patent changes the operational parameter of the clock divider from fixed single-edge awareness to variable edge awareness. By modifying the edge detection parameter to respond to both rising and falling edges when dual-edge awareness is enabled, the frequency scaling ratio is increased without fundamentally changing the overall circuit architecture.
2Speed
If a dual-edge aware clock divider is used, then the frequency scaling ratio is increased, but the device complexity increases
Solution Approach 1:
The clock divider is designed with multi-functionality to handle both single-edge and dual-edge awareness operations within a single unified circuit. This universal design allows the same hardware structure to operate in different modes, achieving high frequency scaling ratios when needed while avoiding the need for separate dedicated circuits for each mode.
Solution Approach 2:
The circuit incorporates dynamic control mechanisms that allow it to switch between operational modes based on requirements. The dual-edge aware clock divider can dynamically adjust its edge response behavior, enabling it to achieve higher frequency scaling ratios only when necessary, thereby managing complexity effectively.
3Use of energy by moving object
If the output clock frequency is limited, then the power consumption of cores is reduced, but the operational performance of high-frequency cores is degraded
Solution Approach 1:
The clock distribution system provides different clock frequencies to different cores based on their specific requirements. High-performance cores that can operate at higher frequencies receive appropriate clock speeds to maintain productivity, while other cores receive lower frequencies to optimize power consumption. This localized quality approach ensures each core operates at its optimal frequency.
Solution Approach 2:
The system dynamically adjusts clock frequencies provided to different cores based on their operational requirements and power constraints. The dual-edge aware clock divider enables flexible frequency generation that can be adapted in real-time to match the performance needs of individual cores, balancing power consumption and productivity dynamically.
Data Source
AI summary
A dual-edge aware clock divider configured to generate an output clock based on the input clock and a ratio of an integer M over an integer N is disclosed herein. The frequency of the output clock is based on a frequency of the input clock multiplied by the ratio (M/N), wherein M may be set to a range up to N. The output clock includes M pulses within a sequence time window having a length of N periods of the input clock. The output clock includes one or more rising edges that are substantially time aligned with one or more rising edges and one or more falling edges of the input clock, respectively. The dual-edge aware clock divider is configured to generate the output clock based on inverted and non-inverted portions of the input clock. A hybrid clock divider including the dual-edge and single-edge aware techniques is provided.