Dual-Edge Clock Error Detection Without Detector Mismatch
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Solution Overview
Problem
Existing clock-tracking circuits face reduced performance due to mismatch between rising-edge triggered and falling-edge triggered phase-frequency detectors, leading to degraded jitter and spur performance.
Innovation Solution
A dual-edge error detection circuit that utilizes a single error detector triggered on both rising and falling edges of clock signals, employing multiplexers to alternately provide inverted and non-inverted clock signal versions to the detector, thereby reusing the detector for both edges and avoiding the need for separate detectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate rising-edge and falling-edge triggered phase-frequency detectors are used, then both edges can be detected, but mismatch between the detectors degrades jitter and spur performance
Solution Approach 1:
The patent combines rising-edge and falling-edge detection capabilities into a single phase-frequency detector by using multiplexers to alternately connect the detector to inverted and non-inverted clock signals. This merging eliminates the mismatch problem between separate detectors while maintaining dual-edge detection functionality.
Solution Approach 2:
The single phase-frequency detector is made universal by enabling it to detect both rising and falling edges through multiplexer switching. The detector performs multiple functions (rising-edge detection and falling-edge detection) using the same hardware component, avoiding the need for separate specialized detectors.
2Device complexity
If a single error detector is reused for both rising and falling edges, then detector complexity is reduced, but the detector must be triggered on both edges
Solution Approach 1:
The system dynamically switches the detector's triggering behavior by using multiplexers to alternately connect inverted and non-inverted clock signals based on the detection phase. This dynamic switching enables the single detector to adaptively respond to both rising and falling edges without requiring hardware changes.
Solution Approach 2:
Multiplexers serve as intermediary components between the clock signals and the single error detector. These intermediaries enable the detector to access both inverted and non-inverted signal versions, providing the versatility needed for dual-edge triggering while keeping the detector itself simple and unified.
3Productivity
If dual-edge error detection is implemented, then error detection capability is doubled, but the circuit requires multiplexers and control logic
Solution Approach 1:
The dual-edge detection function is segmented into distinct operational phases: rising-edge detection using non-inverted signals and falling-edge detection using inverted signals. The multiplexers enable clean segmentation of these detection phases, allowing the single detector to systematically process both edge types with doubled detection capability.
Data Source
AI summary
One or more examples relate to triggering a single error detector on rising and falling edges of clock signals, and generating an error signal therefrom. A method may include receiving a first clock signal and a second clock signal. The method may include generating, via a single error detector being triggered at least partially responsive to like respective edges of the first clock signal and the second clock signal, an error signal that represents a phase difference between the first clock signal and the second clock signal.