Dual-Edge Triggered Clock Gater Circuitry
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Solution Overview
Problem
Dual-edge triggered clock gaters face challenges in balancing clock signal delays between inverting and non-inverting modes, leading to unbalanced clock signals and increased power consumption due to feedback loops.
Innovation Solution
The implementation of dual-edge triggered clock gater circuitry with storage elements, multiplexers, and buffering circuitry that selectively generates output signals based on control signals, reducing power consumption and balancing clock delays by eliminating the need for feedback loops and using controlled delay circuits to adjust clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-edge triggered clock gaters operate in different operational modes (inverting and non-inverting), then the clock gater can serve different circuit portions, but different delay occurs in different operational modes resulting in unbalanced clock signals
Solution Approach 1:
The patent uses feedback loops that sense the output clock signal and adjust the delay of subsequent clock gaters to match the delay of previous gaters. This feedback mechanism dynamically compensates for delay variations between inverting and non-inverting modes, ensuring balanced clock signals across different operational modes while maintaining adaptability.
Solution Approach 2:
The patent implements dynamic delay adjustment where the delay of clock gaters is not fixed but can be modified based on the operational mode and feedback from previous stages. This dynamic adaptation allows the system to maintain balanced clock signals despite operating in different inverting and non-inverting modes.
2Adaptability or versatility
If clock gaters are distributed throughout the clock tree to allow gating at different granularities, then clock gating flexibility is improved, but device complexity increases
Solution Approach 1:
The patent designs a universal clock gater cell that can function in both inverting and non-inverting modes and can be distributed throughout the clock tree. This multi-functional design allows the same basic circuit structure to provide clock gating at different granularities without increasing complexity, as each gater instance is self-contained and can operate independently in either mode.
Solution Approach 2:
The patent divides the clock distribution system into multiple independent clock gater instances distributed throughout the clock tree. Each gater is a discrete, modular unit that can be individually controlled, allowing flexible gating at different granularities while keeping each individual gater's complexity manageable through standardization.
3Manufacturing precision
If feedback loops are used to balance clock delays, then clock signal balance is improved, but switching power consumption increases
Solution Approach 1:
The patent performs delay balancing in advance by pre-characterizing the delay of inverting and non-inverting modes and configuring the feedback loops accordingly. This preliminary action allows the system to achieve balanced clock signals without requiring continuous high-power feedback adjustments during operation, reducing switching power consumption while maintaining precision.
Data Source
AI summary
Techniques are disclosed relating to dual-edge triggered clock gater circuitry. In some embodiments, an apparatus includes dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal. In some embodiments, the clock gater circuitry includes first and second storage elements. In some embodiments, the clock gater circuitry includes multiplexer circuitry that selects between outputs of the first and second storage elements to generate the output signal. In some embodiments, the clock gater circuitry includes a third storage element configured to store an indication of which of the first and second storage elements stores a first digital value and which stores an inverse of the first digital value when not gating. In some embodiments, the clock gater circuitry includes a buffering element configured, when gating, to copy data stored in one of the first and second storage elements to the other of the first and second storage elements.