Dual-Edge Clock Gating That Prevents Missing or Extra Edges
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Solution Overview
Problem
Conventional gated single-edge clock signal generators for dual-edge triggered circuits face functional limitations, including loss or extra unwanted clock signal edges, leading to complexity and increased cost when attempting to avoid these issues.
Innovation Solution
A clock signal generator that uses asymmetric Muller C-elements and logic gates to generate a gated clock signal by considering the active-high and complementary clock gating signals, ensuring that both edges of the clock signal are properly managed, avoiding missed or unwanted transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional gated single-edge clock signal generator is used with dual-edge triggered circuits, then the device complexity is reduced, but functional reliability deteriorates due to loss or extra unwanted clock signal edges
Solution Approach 1:
The clock signal generation is segmented into two independent paths: one path generates clock edges on the rising edge of the clock signal, and another path generates clock edges on the falling edge of the clock signal. Each path has its own gating control mechanism, allowing independent management of positive and negative edges without interference, thus maintaining functional reliability while keeping the device complexity manageable.
2Loss of energy
If conventional gating methods are used to manage clock signals, then the power consumption is reduced, but manufacturing precision deteriorates due to difficulty in avoiding missed or extra transitions
Solution Approach 1:
The gating control signals are prepared in advance with predetermined timing relationships established before the clock signal edges occur. The control logic pre-configures the gating state based on the desired edge transitions, ensuring that clock edges are neither missed nor generated extra times. This preliminary preparation eliminates the need for complex real-time adjustment mechanisms, maintaining manufacturing precision while keeping power consumption low.
3Productivity
If dual-edge triggering is implemented to double the clocking rate, then productivity is improved, but device complexity increases due to the need for sophisticated gating control
Solution Approach 1:
The gating control mechanism uses asymmetric treatment of rising and falling edges, with each edge type having its own dedicated control path and timing reference. This asymmetric design simplifies the overall control logic compared to a symmetric approach that would require complex coordination between positive and negative edges, thereby maintaining manageable device complexity while achieving doubled clocking rate through dual-edge triggering.
Data Source
AI summary
A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.