Dual-Edge Flip-Flop Clock Gating for Low Duty Cycle Distortion
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Solution Overview
Problem
Existing clock gating circuits for dual-edge-triggered flip-flops face challenges in minimizing duty cycle distortion, which affects the performance of dual-edge-triggered sequential circuits.
Innovation Solution
The proposed solution involves a clock gating circuit that includes a clock selection circuit capable of selecting between non-complementary and complementary clock signals based on a logic level difference signal and an enable signal, thereby minimizing duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a clock gating circuit is used to gate clock signals for power saving, then power consumption is reduced, but duty cycle distortion occurs affecting circuit performance
Solution Approach 1:
The clock gating circuit dynamically adjusts the clock signal phase based on the phase relationship between the input clock signal and the complementary clock signal. The circuit detects whether the complementary clock signal leads or lags the input clock signal and accordingly selects whether to gate the rising edge or falling edge, thereby dynamically adapting to duty cycle variations and minimizing distortion in the output clock signal.
Solution Approach 2:
The circuit employs feedback mechanisms to monitor the phase relationship between clock signals and adjust its gating behavior accordingly. By continuously assessing the relative timing of the complementary clock signal and adjusting the gating decision, the circuit maintains optimal duty cycle performance while achieving power savings through clock gating.
2Productivity
If dual-edge-triggered flip-flops are used to increase data throughput, then productivity is improved, but the circuit becomes more sensitive to duty cycle distortion
Solution Approach 1:
The clock gating circuit dynamically adapts its gating behavior based on the phase relationship between clock signals, allowing dual-edge-triggered flip-flops to operate reliably even when duty cycle varies. By adjusting which edges are gated based on real-time phase detection, the circuit maintains consistent timing relationships that dual-edge-triggered devices require for reliable operation.
Solution Approach 2:
The circuit preemptively compensates for potential duty cycle distortion by detecting phase relationships before they cause problems. By anticipating timing issues and adjusting the gating strategy in advance, the circuit prevents duty cycle distortion from degrading the performance of dual-edge-triggered flip-flops, thereby protecting productivity gains.
Data Source
AI summary
An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.