Dual-Edge Clocking With Adaptive Duty Cycle Correction
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Solution Overview
Problem
Integrated circuits face increased dynamic power consumption due to clocking circuitry, particularly in high-density and high-clock-rate designs, where conventional single-edge clocking schemes are inefficient, leading to significant power wastage.
Innovation Solution
Implementing a dual-edge clocking scheme with phase-locked loops (PLLs) that generate square-wave clock signals and adaptive duty cycle distortion correction circuitry to ensure balanced clock pulses at both rising and falling edges, minimizing duty cycle distortion and optimizing power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional single-edge clocking schemes are used, then circuit operation is simple to implement, but dynamic power consumption increases significantly
Solution Approach 1:
The patent implements dual-edge clocking where pulse latches are triggered by both rising and falling edges of the clock signal. This periodic action on both edges allows the circuit to perform the same amount of work in half the time, effectively reducing the clock frequency and thereby reducing dynamic power consumption by approximately 50% while maintaining the same computational throughput
Solution Approach 2:
The patent introduces adaptive duty cycle distortion correction circuitry that dynamically adjusts the clock signal characteristics. This dynamic adjustment compensates for process, voltage, and temperature variations, ensuring optimal pulse width and timing for both rising and falling edge triggers, thereby resolving the complexity of implementing dual-edge clocking effectively
2Productivity
If clock rate is increased to improve circuit performance, then productivity increases, but dynamic power consumption increases
Solution Approach 1:
By utilizing both rising and falling edges of the clock signal for triggering pulse latches, the circuit achieves the same computational throughput at half the clock frequency. This periodic action on both edges allows maintaining productivity while reducing the clock rate, thereby reducing dynamic power consumption proportionally
Solution Approach 2:
The patent changes the operational parameter from single-edge triggering to dual-edge triggering, which effectively doubles the utilization of each clock cycle. This parameter change allows the circuit to maintain the same effective speed with a lower actual clock frequency, reducing power consumption while preserving productivity
3Manufacturing precision
If pulse width is reduced to improve timing performance, then manufacturing precision improves, but positive-edge and negative-edge pulse widths become unbalanced
Solution Approach 1:
The patent implements feedback-based adaptive duty cycle distortion correction where the actual pulse widths of positive-edge and negative-edge triggers are monitored and compared against target values. The correction circuitry adjusts clock signal parameters in real-time to compensate for imbalances, ensuring both pulse widths remain equal and within specifications despite process variations
Solution Approach 2:
The patent replaces fixed, static clock signal generation with a dynamic correction system that uses control logic to adjust timing parameters. This substitution of rigid mechanical timing with adaptive control allows precise balancing of pulse widths while maintaining tight timing performance
Data Source
AI summary
Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.