Dual-Edge Delay Circuit for Accurate Output Enable Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current delay circuits in slave devices for the SoundWire protocol generate approximate delays, consuming area and power while failing to accurately avoid data hazards due to improper signal timing, which is exacerbated by the modified NRZI encoding scheme with DDR.
Innovation Solution
A delay circuit utilizing two separate shift register chains, clocked by opposite edges of a fast clock, to provide a highly accurate delay for the output enable signal, reducing data hazards while minimizing area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay circuit is used to avoid data hazards caused by improper signal timing, then data hazard avoidance is improved, but area and power consumption increase
Solution Approach 1:
The delay circuit is segmented into two separate shift register chains: a first shift register chain clocked by the positive edge of the fast clock, and a second shift register chain clocked by the negative edge of the fast clock. This segmentation allows each chain to be optimized for specific clock edges, reducing overall power consumption while maintaining accurate delay functionality for data hazard avoidance.
Solution Approach 2:
The circuit utilizes periodic clock edges (positive and negative edges of the fast clock) to drive the shift register chains alternately. This periodic action enables the delay circuit to function with lower average power consumption compared to continuous operation, as each chain is activated only during its corresponding clock edge transitions.
2Reliability
If a delay circuit is used to avoid data hazards caused by improper signal timing, then data hazard avoidance is improved, but device area increases
Solution Approach 1:
The delay circuit is divided into two separate shift register chains, each handling opposite clock edges. This segmentation allows for more efficient space utilization compared to a single large delay circuit, as each chain can be optimized independently and activated alternately, reducing the overall area required while maintaining the necessary delay accuracy.
Solution Approach 2:
The circuit dynamically switches between two shift register chains based on the clock edge being processed. This dynamic operation allows the circuit to achieve accurate delay with reduced area, as not all delay elements need to be active simultaneously, unlike static delay circuits that require all elements to be present in the path at once.
3Use of energy by moving object
If approximate delay is used in the delay circuit, then area and power consumption are reduced, but timing accuracy deteriorates
Solution Approach 1:
The circuit uses periodic clock edges (both positive and negative edges of the fast clock) to drive the shift register chains, ensuring that the delay remains accurately synchronized to the clock signal. This periodic action maintains timing precision while reducing power consumption compared to continuous operation, as the delay is refreshed and maintained through regular clocked transitions rather than requiring high-power continuous adjustment mechanisms.
Data Source
AI summary
Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.