Dual-Edge Digital PLL for High-Bandwidth Stable Phase Detection
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Solution Overview
Problem
Conventional phase locked loops, both analog and digital, have limited bandwidth, typically restricted to 1/10 or less of the reference signal frequency to ensure stability, which restricts the detection velocity of phase and frequency.
Innovation Solution
A digital phase locked loop design that compares both rising and falling edges of a reference signal and a feedback signal, utilizing a time-to-digital converter unit, digital adder, digital loop filter unit, and digitally controlled oscillator to generate specific frequencies based on phase differences between these edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bandwidth of the phase locked loop is widened to enhance detection velocity, then the detection velocity of phase and frequency is improved, but the stability of the phase locked loop deteriorates
Solution Approach 1:
The phase locked loop is segmented into two independent detection paths: one path detects phase difference at the rising edge of the reference signal, and the other path detects phase difference at the falling edge of the reference signal. Each path operates independently with its own phase frequency detector, allowing the system to achieve wider bandwidth while maintaining stability through dual-edge sampling.
2Productivity
If the bandwidth is increased to 1/10 or more of the reference signal frequency, then the detection velocity is enhanced, but the stability assurance becomes difficult
Solution Approach 1:
The system achieves continuous phase detection by utilizing both rising and falling edges of the reference signal. Instead of sampling only once per reference signal period, the dual-edge detection method performs phase comparison twice per period, providing continuous feedback and enabling higher bandwidth operation while maintaining loop stability through increased sampling frequency.
Data Source
AI summary
A digital phase locked loop realizing high bandwidth is disclosed. The digital locked loop generates a first digital code corresponding to a difference between a rising edge of a reference signal and a rising edge of a feedback signal and a second digital code corresponding to a difference between a falling edge of the reference signal and a falling edges of the feedback signal, generates a third digital code by adding the first digital code and the second digital code, generates a first frequency control code at the rising edge of the reference signal and a second frequency control code at the falling edge of the reference signal by filtering the third digital code, outputs a specific frequency depending on the first frequency control code and the second frequency control code.