Dual-Edge Sense-Amplifier Flip-Flop for Low-Power High-Speed Scan
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Solution Overview
Problem
Existing flip-flops in sequential circuits face challenges in achieving high-speed operation at low power consumption and efficient design-for-testability, particularly in systems requiring reduced clock frequencies.
Innovation Solution
The implementation of a dual-edge-triggered flip-flop utilizing two sense amplifiers and a set-reset latch, where each sense amplifier operates on alternating clock phases to generate complementary logic values, coupled with a multiplexer for scan mode functionality, allowing reduced clock frequency and improved power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flip-flops are used to achieve high-speed operation, then speed is improved, but power consumption increases
Solution Approach 1:
The patent employs two sense amplifiers operating on alternating clock phases (first clock signal and second clock signal) to process data. During each clock cycle, one sense amplifier is active while the other is inactive, creating a periodic action pattern. This allows the circuit to achieve high-speed operation by utilizing both rising and falling edges of the clock signal, while reducing power consumption by ensuring only one sense amplifier consumes significant power at any given time.
2Reliability
If conventional flip-flops are used for standard operation, then functional performance is improved, but design-for-testability efficiency worsens
Solution Approach 1:
The patent integrates two operational modes within a single flip-flop circuit: functional mode and scan mode. The first and second sense amplifiers can operate together in functional mode for high-speed data processing, or be selectively configured in scan mode for testability. This multi-functionality allows the same hardware structure to serve both functional performance requirements and design-for-testability requirements without sacrificing either.
Data Source
AI summary
A system includes a first sense amplifier having a first data input, a second data input, a clock input configured to receive a first clock signal, a first output, and a second output. The system also includes a second sense amplifier having a first data input, a second data input, a clock input configured to receive a second clock signal, a first output, and a second output. The first data input of the second sense amplifier is coupled to the first data input of the first sense amplifier, and the second data input of the second sense amplifier is coupled to the second data input of the first sense amplifier. The system also includes a set-reset (S-R) latch coupled to the first output and the second output of the first sense amplifier, and coupled to the first output and the second output of the second sense amplifier.