Dual-Edge Flip-Flop With Conditional Clock-Bar Switching
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Solution Overview
Problem
In system-on-chip (SoC) devices, flip-flops used for low-voltage operation face challenges with power consumption, robustness, and area, particularly due to redundant signal transitions that increase power consumption unnecessarily.
Innovation Solution
A dual-edge-triggered flip-flop is designed with an input logic circuit that generates a clock bar signal which maintains a uniform value when the output data bit does not change, preventing redundant transitions and optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a conventional flip-flop is used for low-voltage operation, then the operation voltage can be reduced, but power consumption increases due to redundant signal transitions
Solution Approach 1:
The clock bar signal generation is made dynamic by conditioning it on both the clock signal and the output data bit. The input logic circuit generates the clock bar signal selectively - only when the output data bit changes value. This dynamic behavior allows the flip-flop to adapt its internal signaling to the actual data transition requirements, preventing redundant transitions and reducing power consumption while maintaining low-voltage operation capability
Solution Approach 2:
The patent changes the parameter of the clock bar signal from a simple inverted clock waveform to a conditionally generated signal whose transitions are controlled by the output data bit state. This parameter change in signal generation logic eliminates unnecessary transitions, directly reducing dynamic power consumption while preserving the low-voltage operational characteristic
2Productivity
If the clock bar signal transitions redundantly, then the clock signal can drive the latches, but power consumption increases unnecessarily
Solution Approach 1:
The input logic circuit uses feedback from the output data bit to control the generation of the clock bar signal. By monitoring the output data bit state and only generating clock bar transitions when actual data changes occur, the system provides feedback-based control that eliminates redundant signaling while maintaining necessary clock-driven latch operation
Solution Approach 2:
Instead of generating clock bar transitions for every clock cycle (excessive action), the patent applies partial action by generating transitions only when the output data bit actually changes. This selective approach maintains sufficient clock driving capability for proper latch operation while eliminating unnecessary transitions that would increase power consumption
Data Source
AI summary
A flip-flop includes an input logic circuit, a first latch, a second latch, and an output multiplexer; where the input logic circuit outputs a clock bar signal based on an input data bit and a clock signal, where the first latch and the second latch operate based on the input data bit, the clock signal, and a clock bar signal, where the output multiplexer operates based on outputs from nodes of the first and second nodes and outputs an output data bit, and where the input logic circuit has a uniform value in a period where there is no change of a value of the output data bit.