Dual-Edge Flip-Flop Circuit Using Delayed Clock Latching
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Solution Overview
Problem
Double edge triggered flip flops require significantly more area on integrated circuits and utilize pulses for timing, which can lead to increased area requirements and poor signal transmission.
Innovation Solution
A dual edge triggered flip flop design that combines three portions of circuitry, using delayed clock signals to alternate data latching on both rising and falling edges of the clock, reducing the need for additional pulse generators and optimizing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If double edge triggered flip flop design is implemented, then data rate is doubled or clock rate is reduced, but area requirement increases significantly
Solution Approach 1:
The patent merges the pulse generation function into the existing clock signal distribution network by using clock enable signals that are already generated by the clock manager. Instead of adding dedicated pulse generators to each DET flip flop, the design reuses the clock enable infrastructure to provide the necessary timing signals, thereby achieving double edge triggering without proportionally increasing circuit area.
2Reliability
If pulse generators are added to each DET flip flop, then timing control is improved, but area requirement and device complexity increase
Solution Approach 1:
The clock enable signals serve multiple functions: they act as timing references for double edge detection, function as enable signals for data latching, and provide synchronization across the flip flop array. This multi-functionality eliminates the need for separate dedicated pulse generators, reducing both area and complexity while maintaining reliable timing control.
Solution Approach 2:
The DET flip flop design uses the clock enable signals that are already present in the system architecture to provide its own timing control. Each flip flop self-generates or receives its timing signals from the shared clock enable network, eliminating the need for external or dedicated pulse generation circuitry.
Data Source
AI summary
A dual edge triggered flip flop circuit uses clock signals that are delayed from a first clock signal and from one another by respective intervals. A first set of the plurality of clock signals are used to operate a first latch circuit to allow first data to be conducted to a storage element for a period of time after a rising edge of a first clock signal. The clock signals are further used to operate a second latch circuit to allow second data to be conducted to the storage element for a period of time after a falling edge of the first clock signal.