Dual-Edge Programmable Frequency Divider for Low-Noise Synthesis
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Solution Overview
Problem
Existing variable digital frequency dividers face limitations in efficiently generating a broad range of output frequencies with low power consumption, high efficiency, and low phase noise, particularly in synthesizing frequencies that require rapid selection of signals from a multi-phase clock source.
Innovation Solution
A variable digital frequency divider that calculates and selects the next signal during a single clock pulse, using a logic unit and N-phase signal source, where the frequency control word determines the output frequency relationship as fout=N*fsrc/D, allowing for efficient generation of frequencies by iteratively calculating and selecting bit streams in a digital feedback loop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional variable digital frequency dividers are used to generate a broad range of output frequencies, then frequency versatility is improved, but power consumption increases and phase noise performance deteriorates
Solution Approach 1:
The logic unit calculates the next signal address in advance during the high period of the current clock cycle, before the next clock edge arrives. This preliminary calculation allows the system to be ready for the next signal selection without requiring additional processing time or complex circuitry, thereby maintaining frequency versatility while reducing power consumption through efficient timing.
Solution Approach 2:
The system dynamically adjusts the signal selection based on the frequency control word and current phase, using a programmable division ratio N/D. The logic unit continuously updates the next address calculation based on the frequency control word, enabling flexible frequency synthesis while maintaining low power operation through optimized digital logic switching.
2Adaptability or versatility
If traditional variable digital frequency dividers are used to generate a broad range of output frequencies, then frequency versatility is improved, but phase noise performance deteriorates
Solution Approach 1:
By calculating the next signal address in advance during the high period of the current clock, the system ensures that the address calculation is completed before the next clock edge. This timing approach synchronizes the digital logic operations with the clock phases, minimizing timing jitter and reducing phase noise in the synthesized frequency output.
Solution Approach 2:
The system uses a feedback mechanism where the logic unit continuously calculates the next address based on the frequency control word and current phase state. This closed-loop approach ensures accurate phase alignment and frequency synthesis, maintaining low phase noise while providing broad frequency versatility through programmable control.
3Productivity
If signal selection from multi-phase clock is performed rapidly, then frequency synthesis capability is improved, but device complexity increases
Solution Approach 1:
The next signal address is calculated in advance during the high period of the current clock cycle, before the next clock edge arrives. This preliminary calculation eliminates the need for complex real-time computation circuits, as the address is already prepared when needed. The approach achieves rapid signal selection through efficient timing rather than complex hardware.
Solution Approach 2:
The logic unit uses simple digital logic to calculate the next address by adding the frequency control word to the current address and taking the modulo N. This mathematical operation is implemented using basic digital circuits (adders and counters) rather than complex signal processing hardware, achieving rapid selection with minimal device complexity.
Data Source
AI summary
A dual-edge triggered variable frequency divider for use in digital frequency synthesis is disclosed. The variable frequency divider utilizes a multiphase clock and a logic unit, including both positive and negative edge triggered unit delay elements connected in parallel. The variable frequency divider generates a clock pulse from a signal source that corresponds to an input value from a logic unit, generates a next input value by the logic unit based on the input value and a frequency control word, and transmits the next input value from the logic unit to the signal source in response to the clock pulse. The multiphase clock is configured to generate the clock signal in response to the falling edge of the first pulse of the clock signal. Iteratively selecting signals by this process results in an observed output frequency of fout=N*fsrc/D, where fsrc is the input signal frequency, N is the number of phases of the multi-phase (N-phase) clock, and D is an integer between 1 and N configured by the frequency control word.