Dual-Edge Latch Structure for 50% Duty Odd Frequency Division
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Solution Overview
Problem
Existing frequency dividers, particularly those with odd division numbers, restrict frequency choices due to pulse width limitations, making it difficult to achieve a fifty percent duty cycle, which is essential for various electronic devices like cellular telephones and personal digital assistants.
Innovation Solution
A latch structure that transitions on both rising and falling edges of the input, allowing frequency dividers to operate more flexibly and maintain voltage levels, enabling the use of odd number dividers without restricting frequency choices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing frequency divider circuits are used with odd division numbers, then the circuit structure is simple, but the frequency choices are restricted and fifty percent duty cycle cannot be achieved
Solution Approach 1:
The latch is divided into two separate circuits: a first circuit that drives the first output and a second circuit that drives the second output. Each circuit independently responds to clock edges, allowing flexible frequency division while maintaining simple individual circuit structures. This segmentation enables the system to achieve 50% duty cycle and support odd division numbers without increasing overall complexity.
Solution Approach 2:
The latch structure is designed to respond to both rising and falling edges of the clock signal, making it universally applicable for different division ratios including odd numbers. The dual-circuit design allows the same latch structure to achieve various duty cycles and frequency divisions, eliminating the restriction to integer multiples of input period and enabling 50% duty cycle operation.
2Ease of operation
If conventional latch structures are used, then the circuit design is straightforward, but the output pulse widths are restricted to integer multiples of input period
Solution Approach 1:
The latch transitions dynamically on both rising and falling edges of the input clock signal, rather than being restricted to a single edge type. This dynamic response allows the output pulse widths to be precisely controlled to achieve 50% duty cycle and supports flexible frequency choices including odd division numbers, while maintaining straightforward circuit operation through conventional latch design principles.
3Adaptability or versatility
If the latch transitions only on single edges, then the circuit operation is simple, but the frequency divider cannot achieve fifty percent duty cycle with odd division numbers
Solution Approach 1:
The latch is divided into two separate circuits: a first circuit that drives the first output and a second circuit that drives the second output. Each circuit independently responds to clock edges, allowing flexible frequency division while maintaining simple individual circuit structures. This segmentation enables the system to achieve 50% duty cycle and support odd division numbers without increasing overall complexity.
Solution Approach 2:
The latch transitions dynamically on both rising and falling edges of the input clock signal, rather than being restricted to a single edge type. This dynamic response allows the output pulse widths to be precisely controlled to achieve 50% duty cycle and supports flexible frequency choices including odd division numbers, while maintaining straightforward circuit operation through conventional latch design principles.
Data Source
AI summary
A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.