Dual Edge Memory Clock Generation Circuit
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Solution Overview
Problem
Single clock edge triggered synchronous integrated circuits dissipate power due to clock edge propagation, and dual edge clocked systems with external edge detectors incur a power and performance penalty, while implementing two clock trees is complex.
Innovation Solution
A dual clock edge triggered memory circuitry that generates internal clock edges in response to both rising and falling edges of the system clock, using an internal clock generating circuitry with pulse generation and edge detection, allowing self-timed reset events and efficient operation on both clock edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If external edge detectors are used to enable dual edge clocked operation, then power consumption per operation is reduced, but power and performance penalties are incurred
Solution Approach 1:
The edge detection functionality is extracted from external components and integrated directly into the memory device's internal clock generating circuitry. The internal clock generating circuitry includes edge detection circuits that detect both rising and falling edges of the system clock signal, eliminating the need for external edge detectors and their associated power and performance penalties.
Solution Approach 2:
An internal clock signal is introduced as an intermediary between the system clock and the memory components. The internal clock generating circuitry converts the system clock into an internal clock that is edge-triggered on both rising and falling edges, allowing dual-edge operation without requiring external edge detection circuitry.
2Use of energy by moving object
If two clock trees are implemented for dual edge operation, then power efficiency is improved, but implementation complexity increases
Solution Approach 1:
The clocking function is segmented into internal clock generating circuitry within the memory device rather than requiring separate clock trees. The internal clock generator produces edge-triggered signals internally, eliminating the need for complex dual clock tree implementations while maintaining power efficiency benefits.
Solution Approach 2:
The internal clock generating circuitry serves multiple functions: it receives the system clock, detects both rising and falling edges, generates the internal clock signal, and provides timing control for memory operations. This multi-functional approach replaces the need for separate clock trees while achieving dual-edge operation.
3Device complexity
If single clock edge triggering is used, then clock tree implementation is simplified, but power consumption per operation increases
Solution Approach 1:
The memory device dynamically responds to both rising and falling edges of the system clock through its internal clock generating circuitry. This dynamic dual-edge triggering capability allows the memory to perform operations on both clock edges, effectively doubling the operational frequency and reducing power consumption per operation while maintaining a simple single clock tree structure.
Data Source
AI summary
Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.