Dual-Edge Digital Phase Detector for Accurate Frequency Locking
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Solution Overview
Problem
Conventional digital phase-locked loop (DPLL) circuits face issues with improper frequency locking due to inadequate reset pulse duration, leading to potential locking onto the wrong frequency.
Innovation Solution
A phase detector design that samples clock and reference signals on both positive and negative edges, generating error signals and using OR gates to combine them, along with NAND and AND gates and delay buffers to ensure proper reset and extended reset pulses, ensuring accurate frequency locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the reset pulse duration is reduced to shorten unused time between update periods, then productivity is improved, but reliability deteriorates as flip-flops may not reset properly and the PLL may lock onto wrong frequency
Solution Approach 1:
The patent transitions from single-edge sampling to dual-edge sampling, utilizing both rising and falling edges of clock signals. This dimensional change in sampling approach allows the system to effectively double the update rate while maintaining sufficient reset pulse duration for reliable flip-flop operation, thereby resolving the contradiction between productivity and reliability
Solution Approach 2:
The patent implements periodic reset pulses synchronized with both rising and falling edges of clock signals. By establishing a periodic action pattern that resets flip-flops at regular intervals corresponding to each clock edge, the system ensures reliable resetting while maximizing the update frequency, thus resolving the contradiction between update rate and resetting reliability
2Reliability
If additional capacitors, delay elements and logic differential amplifiers are added to extend reset pulse duration, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent employs self-service by utilizing the existing clock signal edges themselves to trigger the reset operation. The rising and falling edges of the clock signals directly activate the reset logic without requiring external delay elements or additional capacitors, thereby achieving reliable flip-flop resetting while maintaining circuit simplicity and avoiding increased device complexity
Solution Approach 2:
The patent makes the clock signal serve multiple functions: it provides the timing reference for phase comparison and simultaneously serves as the trigger for reset operations. This multi-functionality eliminates the need for separate reset timing circuitry, reducing device complexity while ensuring reliable flip-flop resetting through proper edge detection
Data Source
AI summary
Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector samples the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, samples the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and generates one or more error signals indicating a phase difference between the clock signal and the reference signal. A clock signal that is phase aligned with a reference signal can be generated by generating an error signal indicating a phase difference between the clock signal and the reference signal and applying the error signal to an oscillator to produce the clock signal.