Dual-Edge Phase Locking for Low-Jitter 50% Duty-Cycle Clocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Designing a low jitter fast phase locking synthesizer is challenging due to the intrinsic contradiction between reducing jitter and improving phase tracking and locking, and maintaining a 50% duty-cycle of the clock signal, especially as the oscillating frequency increases, making it difficult for voltage controlled oscillators to operate effectively.
Innovation Solution
The signal generating apparatus utilizes rising and falling edge phase differences to facilitate phase locking, with adjustable bandwidth control and duty-cycle correction, employing detecting circuits, charge pumps, and feedback frequency dividers to input control signals every half cycle, thereby achieving fast phase locking and reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the VCO operates at doubled oscillating frequency to achieve 50% duty-cycle, then the duty-cycle requirement is met, but the VCO becomes hard to oscillate at higher frequencies
Solution Approach 1:
The patent divides the phase detection process into two separate detection circuits: one for rising edges and one for falling edges. This segmentation allows independent optimization of each detection path, enabling the system to maintain 50% duty-cycle accuracy without requiring the VCO to operate at impractically high doubled frequencies.
Solution Approach 2:
The patent introduces edge detection circuits as intermediary components between the VCO output and the phase detector. These detectors convert the high-frequency VCO signal into lower-frequency pulse signals that are easier to process, allowing accurate duty-cycle control without demanding the VCO operate at extremely high frequencies.
2Speed
If the phase locking bandwidth is increased to achieve fast phase locking, then the locking speed improves, but the jitter of the output signal increases
Solution Approach 1:
The patent implements dynamic bandwidth control where the phase detector bandwidth is adjusted based on the locking state. During acquisition, the bandwidth is wider to enable fast locking. Once locked, the bandwidth narrows to reduce jitter. The dual edge detection provides more phase error information that enables this dynamic adaptation.
Solution Approach 2:
The patent uses feedback from both rising and falling edge detections to continuously monitor the phase relationship. This dual-edge feedback mechanism provides more accurate phase error signals that enable the system to achieve fast locking while maintaining low jitter through precise control adjustments.
3Device complexity
If a single phase detector is used to simplify the circuit, then the device complexity is reduced, but the phase detection accuracy and duty-cycle control are compromised
Solution Approach 1:
Instead of using a single complex phase detector, the patent segments the detection function into two simpler detectors: one for rising edges and one for falling edges. Each detector focuses on a specific edge type, achieving higher precision for its designated function while keeping individual detector circuits relatively simple.
Solution Approach 2:
The patent combines the outputs of the rising edge detector and falling edge detector to achieve comprehensive phase detection and duty-cycle control. By merging the information from both edge detections, the system achieves high precision without requiring any single detector to be overly complex.
Data Source
AI summary
The oscillating signal generator utilizes a rising edge phase difference and a falling edge phase difference of the input signal and a feedback signal to generate a rising control signal and a falling control signal, and generates an output signal according to the rising control signal and the falling control signal; wherein the feedback signal corresponds to the output signal.