Dual-Edge Phase-Locked Loop for Wider Stable Bandwidth

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Solution Overview

Problem

The bandwidth of traditional phase-locked loops is limited to 1/10 or less of the reference signal frequency, restricting phase and frequency detection speeds.

Innovation Solution

A phase-locked loop design that compares both rising and falling edges of the reference signal with the feedback signal, using a phase frequency detector, charge pump, loop filter, and voltage control oscillator to generate and control frequency, allowing for increased bandwidth by utilizing both edges for phase difference calculations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the bandwidth of the PLL is widened to improve phase and frequency detection speeds, then the detection speed is improved, but the stability of the PLL deteriorates

Engineering Contradiction:

Improvephase and frequency detection speedVSAvoidstability of the PLL

Core Design Contradiction:

SpeedVSStability of the object's composition

Solution Approach 1:

The phase detection function is segmented into two independent paths: one path detects phase difference using rising edges, and the other path detects phase difference using falling edges. Each path operates independently with its own charge pump, allowing the system to process both edges separately while maintaining stability in each path, thereby enabling wider bandwidth without sacrificing stability.

Inventive Principle:

Principle #1Segmentation

2Stability of the object's composition

If the bandwidth of the PLL is limited to 1/10 or less of the reference signal frequency to secure stability, then the stability is maintained, but the phase and frequency detection speed deteriorates

Engineering Contradiction:

Improvestability of the PLLVSAvoidphase and frequency detection speed

Core Design Contradiction:

Stability of the object's compositionVSSpeed

Solution Approach 1:

The system continuously utilizes both rising edges and falling edges of the reference signal for phase detection, effectively doubling the useful detection opportunities within each reference signal period. This continuous utilization of both edges allows the PLL to achieve wider bandwidth and faster detection speed while maintaining stability through the balanced contribution of both edge types.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS10320400B2Phase-locked loop with high bandwidth using rising edge and falling edge of signal

Publication Date: 2019.06.11 INDUSTRY UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY

AI summary

Disclosed is a phase-locked loop having a high bandwidth using the rising edge and falling edge of a signal. The disclosed phase-locked loop controls the frequency of a voltage control oscillator by comparing both a phase difference between rising edge of a reference signal and rising edge of a feedback signal and a phase difference between falling edge of the reference signal and falling edge of the feedback signal.