Dual-Edge Pulsed Latch Circuit for Lower-Power Clocking
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Solution Overview
Problem
Dual edge triggered clocking schemes in sequential logic circuits face challenges such as increased complexity, power consumption, and slower device performance, while also precluding phase-based designs and requiring precise duty cycle control to avoid clock skew.
Innovation Solution
The development of dual edge triggered pulsed latches that use overlapping clock signals and transparency circuits to become transparent on both edges of the clock, allowing for efficient data storage and reducing power consumption by utilizing implicit or explicit pulse generators to activate the latch at appropriate times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dual edge triggered clocking schemes are used, then power consumption is reduced by distributing clock at half frequency, but sequential circuits become more complicated and power consumption increases
Solution Approach 1:
The circuit is divided into two separate transparent latch circuits (first transparent latch circuit and second transparent latch circuit) that operate on different clock edges. Each latch circuit is independently controlled by clock signals derived from the same clock input, allowing the system to achieve dual-edge triggering while maintaining simplicity in each individual latch unit.
Solution Approach 2:
Two transparent latch circuits are combined in a single flip-flop structure, where the first latch captures data on one clock edge and the second latch captures data on the opposite clock edge. The outputs of both latches are merged to produce the final Q and Qbar outputs, enabling dual-edge triggering functionality while managing complexity through systematic integration.
2Loss of energy
If dual edge triggered clocking schemes are used, then clock distribution power is reduced, but device speed decreases
Solution Approach 1:
The circuit utilizes periodic clock signal transitions (rising and falling edges) to trigger data capture at both edges of the clock cycle. By employing transparent latch circuits that respond to specific clock edge transitions, the system achieves dual-edge triggering that effectively doubles the data capture rate without requiring higher clock frequencies, thus maintaining speed while reducing power.
3Loss of energy
If dual edge triggered clocking schemes are used, then power consumption is reduced, but duty cycle control becomes critical to avoid skew
Solution Approach 1:
An intermediate signal generation stage is introduced that derives complementary clock signals (first clock signal and second clock signal) from a single clock input. This intermediary stage ensures that both latch circuits receive properly phased clock signals with controlled duty cycles, eliminating the need for precise external duty cycle control while maintaining robust operation against duty cycle variations.
4Productivity
If traditional dual edge triggered flip flops are used, then both clock edges are utilized, but phase-based designs are precluded
Solution Approach 1:
The flip-flop design incorporates universal transparent latch circuits that can operate in dual-edge triggered mode while maintaining compatibility with phase-based design methodologies. The latch circuits are designed to be transparent during specific clock phases and opaque during others, enabling the circuit to function as both a dual-edge triggered flip-flop and a phase-based transparent latch depending on the clock signal configuration.
Data Source
AI summary
An implicitly pulsed dual edge triggered pulsed latch. The implicitly pulsed latch includes an overlapping clock generator and a transparency circuit designed to cause a transparent latch circuit to become transparent on each edge of a clock signal. A logic value on the input node of the latch is transferred to the output node of the latch in response to each clock edge transition. An explicitly pulsed dual edge triggered pulsed latch including a pulse generator and a transparent latch circuit. The explicitly pulsed latch includes a symmetrical pulse generator designed to cause the latch circuit to pass a logic value from the input node of the latch to the output node of the latch in response to a pulse on the clock node.