Dual-Edge PWM Controller Dynamic Ramp Signal Response

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Solution Overview

Problem

Conventional power regulators face delays in responding to fast load transitions due to fixed ramp signals in dual-edge modulation schemes, leading to turn-on and turn-off delays that result in undesirable voltage spikes during CPU operations.

Innovation Solution

A dual-edge modulation controller using first and second ramp circuits, comparators, and pulse control logic that generates leading-edge and trailing-edge ramp signals synchronized with clock signals, allowing for dynamic PWM signal control based on feedback and reference signals, thereby reducing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a fixed ramp signal is used in conventional dual-edge modulation, then the modulation scheme is simple to implement, but turn-on and turn-off delays occur that prevent timely response to fast load transitions

Engineering Contradiction:
Improveresponse speed to load transitionsVSAvoidturn-on and turn-off delays
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the ramp signal variable rather than fixed. The ramp signal is dynamically adjusted based on the PWM signal state - it ramps up during the on-period and ramps down during the off-period. This dynamic adaptation allows the modulation scheme to respond immediately to load transitions without the delays inherent in fixed ramp signals, directly resolving the contradiction between response speed and time delay.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If leading-edge modulation is used, then response to load-adding transients is improved, but response to load-releasing transients is poor

Engineering Contradiction:
Improveresponse to different transient typesVSAvoidresponse speed to load-releasing transients
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent implements universality by creating a modulation scheme that handles both load-adding and load-releasing transients effectively. The dual-edge modulation with dynamic ramp signals allows the system to respond quickly to both types of transients - the leading-edge responds to load-adding while the trailing-edge responds to load-releasing. This multi-functional capability resolves the contradiction by making the system adaptable to different transient types without sacrificing response speed in either case.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If trailing-edge modulation is used, then response to load-releasing transients is improved, but response to load-adding transients is poor

Engineering Contradiction:
Improveresponse to different transient typesVSAvoidresponse speed to load-adding transients
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent achieves universality by combining both leading-edge and trailing-edge modulation capabilities in a single system. The dynamic ramp signal approach enables the trailing-edge to respond quickly to load-releasing transients while the leading-edge simultaneously provides fast response to load-adding transients. This resolves the contradiction by making the system universally effective for both transient types rather than optimizing for one at the expense of the other.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7453250B2PWM controller with dual-edge modulation using dual ramps
Publication Date: 2008.11.18 INTERSIL AMERICAS INC
  • US7453250B2 patent drawing
  • US7453250B2 patent drawing
  • US7453250B2 patent drawing

AI summary

A dual-edge modulation controller including first and second ramp circuits, first and second comparators, an error amplifier and pulse control logic. The first ramp circuit provides a leading-edge ramp synchronous with a clock. The error amplifier compares a feedback signal with a reference and provides a compensation signal. The first comparator compares the leading-edge ramp with the compensation signal and asserts a set signal. The second ramp circuit provides a trailing-edge ramp that begins ramping when the set signal is asserted. The second comparator compares the trailing-edge ramp with the compensation signal and asserts a reset signal. The pulse control logic asserts a PWM signal when the set signal is asserted and de-asserts the PWM signal when the reset signal is asserted. The controller may control multiple phases with current balancing. The slew rate of the ramps may be adjusted based on the number of PWM signal asserted.