Serial-to-Parallel Conversion Circuit Using Dual-Edge Data Latching
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Solution Overview
Problem
Conventional serial-to-parallel conversion circuits face a race condition issue when implementing IEEE 1355, IEEE 1355.2, and IEEE 1394 standards, which limits reception speed and is difficult to implement with general-purpose programmable semiconductor devices like CPLDs or FPGAs due to the need for delay circuits.
Innovation Solution
A method is introduced where a clock generator produces a clock by taking the exclusive OR of received data and strobe, and a register group latches data synchronously with both the rising and falling edges of the clock, using a logical circuit to delay data latch timing and eliminate the race condition without requiring delay circuits, thereby increasing data reception speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay circuit is provided to eliminate the race condition, then the reliability is improved, but the reception speed is limited and the device complexity increases
Solution Approach 1:
The patent applies preliminary action by determining a rule about data and strobe logical values before the latching operation occurs. The logical circuit is designed in advance to generate outputs that conform to this rule, ensuring that data changes are completed before the clock edge arrives at the flip-flop, thereby preventing race conditions without requiring delay circuits.
Solution Approach 2:
The patent changes the parameter of data latch timing by using both rising and falling edges of the clock signal for latching operations. This dual-edge latching approach effectively doubles the data transmission capacity within the same clock period, increasing reception speed while maintaining reliability through the predetermined logical circuit design.
2Reliability
If a delay circuit is provided to eliminate the race condition, then the reliability is improved, but general-purpose programmable semiconductor devices cannot be used
Solution Approach 1:
The patent determines a rule in advance about the relationship between data and strobe logical values before latching. The logical circuit is designed to conform to this rule, eliminating the need for delay circuits that cannot be implemented in programmable devices. This approach enables reliable race condition prevention using only standard logic circuits available in CPLDs and FPGAs.
3Reliability
If the clock phase is delayed by providing a delay circuit, then the race condition is eliminated, but the maximum reception speed is limited
Solution Approach 1:
Instead of delaying the clock, the patent determines a rule in advance and designs the logical circuit to ensure data is ready before the clock edge. This preliminary preparation of data according to the predetermined rule eliminates race conditions without slowing down the clock signal, thereby maintaining maximum reception speed.
Solution Approach 2:
The patent utilizes both rising and falling edges of the clock signal for latching operations, effectively doubling the utilization of the clock period. This periodic action on both edges allows higher reception speed while the predetermined logical circuit design ensures race condition-free operation without requiring clock delay.
Data Source
AI summary
The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data and a strobe when a first-stage memory device in a shift register latches data and when the memory device holds the data; providing a logical circuit for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.