Dual-Edge Triggered Ring Buffer Timing Control
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Solution Overview
Problem
The synchronization issue between clocks of two systems during data transmission leads to conflicts between register setup and hold times, complicating the timing of data transmission in existing ring buffer systems.
Innovation Solution
A dual-edge triggered ring buffer with a two-step data writing mode, utilizing a logic clock generation module to generate first and second logic clock signals, which control the data writing module to write data at specific clock edges, reducing timing complexity and avoiding conflicts between register setup and hold times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dual-edge triggered buffer is adopted to maximize data transmission at rising and falling edges, then data transmission efficiency is improved, but timing complexity increases and synchronization issues arise due to conflicts between register setup time and hold time
Solution Approach 1:
The patent segments the data transmission process into two distinct steps: a first step for writing data to the buffer and a second step for reading data from the buffer. This segmentation allows each step to be triggered by different clock edges (rising edge for writing, falling edge for reading), thereby avoiding timing conflicts between setup and hold times while maintaining dual-edge triggering efficiency.
2Reliability
If a ring buffer is configured to coordinate data transmission when clocks are out of sync, then synchronization between systems is improved, but the relative arrangement between incoming data and clock edges becomes complex, causing timing conflicts
Solution Approach 1:
The patent extracts the timing control logic from the data path by using separate trigger inputs for the first and second steps. The first trigger input controls the write operation independently from the second trigger input that controls the read operation. This extraction simplifies the timing arrangement by decoupling the clock edge requirements for writing and reading, while still maintaining synchronization between systems with different clock phases.
Data Source
AI summary
The present disclosure provides a dual-edge triggered ring buffer and a communication system. The dual-edge triggered ring buffer includes a logic clock generation module and a data writing module. The logic clock generation module is configured to generate a corresponding first logic clock signal upon detecting an input of the trigger signal corresponding to the multiple first trigger signal input terminals, or to generate a corresponding second logic clock signal upon detecting an input of the trigger signal corresponding to the multiple second trigger signal input terminals. The data writing module is configured to write data output from the external system through the multiple corresponding input terminals according to the first logic clock signal or the second logic clock signal.