Dual Encapsulation for MRAM Sidewall Protection
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Solution Overview
Problem
Current methods for integrating magnetic random access memory (MRAM) structures into sub-100 nanometer CMOS logic devices face challenges such as damage during back-end-of-line (BEOL) processing and degradation of inter-level dielectrics due to exposed sidewalls and contaminants from the etching process, especially when integrating with fine-pitch interconnects.
Innovation Solution
The implementation of a dual encapsulation layer scheme using silicon nitride material along the sidewalls of MRAM structure components, including a first encapsulation layer for the free and top electrodes and a second encapsulation layer for the bottom and fixed electrodes, to protect these components from damage during BEOL processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MRAM structures are integrated into sub-100 nm CMOS devices with common BEOL interconnects, then integration density is improved, but the MRAM structures become susceptible to damage during BEOL processing and inter-level dielectrics degrade due to exposed sidewalls and etching contaminants
Solution Approach 1:
Encapsulation layers are formed over the MRAM structures before BEOL processing begins. This preliminary protective action prevents damage to exposed sidewalls and blocks contaminants from etching processes from reaching and degrading the inter-level dielectrics, thereby maintaining reliability while enabling high-density integration
Solution Approach 2:
The encapsulation layers serve as intermediary protective barriers between the MRAM structures and the harsh BEOL processing environment. These layers mediate the interaction by shielding the sensitive MRAM components from damage and preventing contaminant migration, thus resolving the contradiction between integration density and structural integrity
2Manufacturing precision
If MTJ stack sidewalls are exposed after etching to form magnetic layers, then manufacturing precision is improved, but the exposed sidewalls are damaged during subsequent BEOL processing
Solution Approach 1:
Encapsulation layers are deposited conformally over the MTJ stack structures before BEOL processing. This preliminary protective coating preserves the precisely formed sidewalls by shielding them from mechanical and chemical damage during subsequent interconnect fabrication steps
Solution Approach 2:
Thin film encapsulation layers are formed over the MTJ stack sidewalls, providing a protective shell that maintains the precision of the etched features while protecting against damage. The thin film nature allows the encapsulation to conform to the sidewall geometry without significantly altering the underlying structure
3Length of moving object
If fine-pitch interconnects are used with MTJ stacks to achieve smaller memory cells, then device miniaturization is improved, but mobile ions and etching contaminants severely degrade the inter-level dielectrics
Solution Approach 1:
The encapsulation layers act as intermediary barriers that prevent mobile ions and etching contaminants from reaching and degrading the inter-level dielectrics. This mediation enables the use of fine-pitch interconnects for miniaturized memory cells while protecting the dielectric quality from contamination
Solution Approach 2:
The encapsulation structure extracts or isolates the harmful etching contaminants and mobile ions from the vicinity of the inter-level dielectrics, preventing their harmful interactions. This extraction enables safe integration of fine-pitch interconnects without dielectric degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively shields MRAM structures from BEOL process-related damage, enabling reliable integration with sub-100 nm CMOS devices by reducing the susceptibility to sidewall damage and contaminant-induced degradation, thus enhancing yield and reliability.
Implementation Method 1
a first encapsulation layer disposed along the free layer sidewalls and the top electrode sidewalls and a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls
Data Source
AI summary
Integrated circuits with magnetic random access memory (MRAM) and dual encapsulation for double magnesium oxide tunnel barrier structures and methods for fabricating the same are disclosed herein. As an illustration, an integrated circuit includes a magnetic random access memory structure that includes a bottom electrode that has a bottom electrode width and has bottom electrode sidewalls and a fixed layer overlying the bottom electrode that has a fixed layer width that is substantially equal to the bottom electrode width and has fixed layer sidewalls. The MRAM structure of the integrated circuit further includes a free layer overlying a central area of the fixed layer. Still further, the MRAM structure of the integrated circuit includes a first encapsulation layer disposed along the free layer sidewalls and a second encapsulation layer disposed along the bottom electrode sidewalls and the fixed layer sidewalls.