Dual-End Bit Line Charging in NAND Flash Memory

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Solution Overview

Problem

The miniaturization of semiconductor storage devices leads to increased wiring width and resistance in bit lines, prolonging charging times, especially when charging is done from only one side, which affects the performance of NAND flash memory systems.

Innovation Solution

Incorporating a bit line charging circuit at the opposite end of each bit line, allowing simultaneous charging from both ends by the sense amplifier and the bit line charging circuit, reducing charging time and maintaining a smaller circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the bit line is charged from only one side, then the circuit area is kept small, but the charging time is prolonged due to increased wiring width and resistance

Engineering Contradiction:

Improvecircuit areaVSAvoidcharging time

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The bit line charging function is segmented into two independent charging paths: one from the sense amplifier at one end and another from the bit line charging circuit at the opposite end. This segmentation allows simultaneous charging from both ends, effectively halving the charging time while maintaining compact circuit area through functional division.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The charging approach transitions from one-dimensional (single-end charging) to two-dimensional (dual-end charging) by adding a charging circuit at the opposite end of the bit line. This dimensional change in the charging architecture enables parallel charging paths without significantly increasing the overall circuit footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If the bit line charging circuit is added at the opposite end, then the charging speed is improved, but the circuit area may increase

Engineering Contradiction:

Improvecharging speedVSAvoidcircuit area

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The bit line charging circuit is implemented with local quality optimization by using transistors sized appropriately for the specific charging requirements at each bit line location. This allows the charging circuit to achieve high charging speed while minimizing the area occupied by the charging circuit components through localized transistor sizing and placement.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The bit line charging circuit is designed with multi-functionality to serve multiple purposes: it charges the bit line during read operations, assists during write operations, and can be controlled to operate only when needed. This universal design allows the same circuit structure to perform multiple functions without requiring separate dedicated circuits for each operation, thereby reducing overall circuit area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9653174B2Semiconductor storage device

Publication Date: 2017.05.16 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor storage device includes memory cell array including a memory cell, a bit line coupled to the memory cell, a sense circuit coupled to the bit line and being capable of charging the bit line, and a charging circuit, the memory cell array being disposed between the sense circuit and the charging circuit and being capable of charging the bit line.