Dual Epi Process Void Prevention in Semiconductor Devices
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Solution Overview
Problem
Current techniques for performing dual epitaxial processes in semiconductor devices are unsatisfactory, often resulting in voids between the gate structure and strained source/drain features, which degrade device performance.
Innovation Solution
A method involving the formation of gate structures, spacers, capping layers, and protection layers on a semiconductor substrate, followed by selective etching and epitaxial growth to minimize void formation, including specific steps such as forming spacers, capping layers, protection layers, and selective etching to expose substrate portions for epitaxial growth, ensuring precise control over the growth of semiconductor materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional dual epi process techniques are used, then epitaxial growth can be performed for both n-type and p-type devices, but voids are formed between the gate structure and strained source/drain features
Solution Approach 1:
The patent divides the dual epi process into separate sequential steps with distinct capping and protection layer removal for n-type and p-type devices. This segmentation allows independent control of each device type's epitaxial growth, preventing void formation while maintaining dual device fabrication capability.
Solution Approach 2:
The patent applies preliminary protective capping layers and protection layers before epitaxial growth. These layers are strategically removed only where needed, preventing unwanted growth and void formation. The preliminary action of forming these protective structures enables precise control over where epitaxial material grows, eliminating the voiding problem.
2Manufacturing precision
If selective etching is used to remove capping layers, then precise control over epitaxial growth locations is achieved, but process complexity increases
Solution Approach 1:
The patent employs selective etching processes that exhibit different etching rates for different materials at different locations. The etching process is tailored to remove specific capping layers (e.g., silicon nitride) while leaving others (e.g., silicon oxide) intact in certain regions. This local differentiation enables precise spatial control over epitaxial growth without requiring excessively complex multi-step procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the risk of void formation between the gate structure and strained source/drain features, enhancing device performance by ensuring accurate epitaxial growth and minimizing defects.
Implementation Method 1
an etching process that exhibits an etching selectivity of the second material to the first material
Implementation Method 2
epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region
Data Source
AI summary
The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.