Dual Etch-Stop Stack for Via Misalignment and Dielectric Protection
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Solution Overview
Problem
In integrated chips, misalignment during the formation of metal vias can damage the underlying dielectric layers, leading to reduced reliability and increased capacitance, which negatively impacts the chip's performance due to a decrease in the lateral distance between metal wires.
Innovation Solution
A dual etch-stop layer configuration is implemented, where a first etch-stop layer is used to prevent damage to the dielectric layer by maintaining a selective etch rate difference between the etch-stop layers, thereby preventing misalignment damage and maintaining the lateral distance between metal wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single etch-stop layer is used during metal via formation, then the manufacturing process is simpler, but misalignment during etching can damage the underlying dielectric layer, reducing reliability
Solution Approach 1:
The patent divides the single etch-stop layer into two separate etch-stop layers (first etch-stop layer and second etch-stop layer) with different etch selectivities. The first etch-stop layer has lower etch selectivity to the etchant than the second etch-stop layer, creating a segmented structure that provides different protection levels at different depths, thereby preventing misalignment damage while maintaining manufacturing feasibility
Solution Approach 2:
The first etch-stop layer acts as an intermediary protective layer between the second etch-stop layer and the underlying dielectric layer. During the etching process, if misalignment occurs, the first etch-stop layer serves as a sacrificial barrier that prevents the etchant from reaching and damaging the critical dielectric layer, thus mediating the protection function
2Reliability
If misalignment damage occurs to the dielectric layer, then the lateral distance between metal wires decreases, but capacitance increases, negatively impacting chip performance
Solution Approach 1:
The dual etch-stop layer structure provides beforehand cushioning by creating a protective buffer zone. The first etch-stop layer, positioned closer to the dielectric layer, absorbs potential misalignment errors before they can cause damage. This prior cushioning prevents the harmful effect of increased capacitance by maintaining the intended lateral distance between metal wires
3Reliability
If the etch selectivity difference between etch-stop layers is increased, then protection against misalignment is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent changes the material composition parameters of the two etch-stop layers to achieve different etch selectivities. By selecting materials with inherently different reactivity to the etchant (first etch-stop layer with lower selectivity, second etch-stop layer with higher selectivity), the system achieves reliable misalignment protection through material parameter selection rather than relying solely on precise geometric control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of the dielectric layer and reduces capacitance, resulting in improved performance by maintaining the integrity of the dielectric layer and minimizing RC delay.
Implementation Method 1
maintaining a selective etch rate difference between the etch-stop layers
Data Source
AI summary
The present disclosure relates to an integrated chip including a substrate. A first conductive wire is within a first dielectric layer that is over the substrate. A first etch-stop layer is over the first dielectric layer. A second etch-stop layer is over the first etch-stop layer. A conductive via is within a second dielectric layer that is over the second etch-stop layer. The conductive via extends through the second etch-stop layer and along the first etch-stop layer to the first conductive wire. A first lower surface of the second etch-stop layer is on a top surface of the first etch-stop layer. A second lower surface of the second etch-stop layer is on a top surface of the first conductive wire.