Dual Etch-Stop Layer Structure for Via Misalignment Protection
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Solution Overview
Problem
Misalignment during the formation of metal vias in integrated chips can damage underlying dielectric layers, leading to reduced reliability and increased capacitance and RC delay, which affects the performance of the integrated chip.
Innovation Solution
Implementing a dual etch-stop layer structure where the second dielectric material is configured to reduce misalignment damage and improve a reliability and performance of the integrated chip. The first and second layers are configured to reduce misalignment damage and improve a reliability of the integrated chip. The first and second dielectric layers are patterned to define a first and second interconnect structure. The first and second layers are configured to reduce capacitance and RC delay of the integrated chip. The first and second layers are patterned to define a second and third capacitance and RC delay of the integrated chip. The first and second capacitance are configured to reduce capacitance and RC delay of the integrated chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single etch-stop layer is used during metal via formation, then the manufacturing process is simpler, but misalignment damage to underlying dielectric layers occurs, reducing reliability
Solution Approach 1:
The single etch-stop layer is segmented into two distinct etch-stop layers with different etch selectivities. The first etch-stop layer has lower etch selectivity relative to the first dielectric layer, while the second etch-stop layer has higher etch selectivity relative to the second dielectric layer. This segmentation allows each layer to protect against misalignment damage at different levels, thereby improving overall dielectric layer reliability without requiring excessive complexity.
Solution Approach 2:
The dual etch-stop layer structure acts as an intermediary protection system between the metal vias and the underlying dielectric layers. By introducing these intermediate layers with graded etch selectivities, the patent creates a buffer zone that absorbs misalignment errors during via formation, preventing direct damage to the critical dielectric layers while maintaining a manageable structural complexity.
2Productivity
If misalignment damage occurs during via formation, then the manufacturing process remains simple, but capacitance and RC delay increase, reducing chip performance
Solution Approach 1:
The patent applies beforehand cushioning by pre-positioning the dual etch-stop layer structure before via formation. This structure provides a protective cushion that absorbs misalignment damage during the via etching process. The first etch-stop layer with lower selectivity cushions against damage to the first dielectric layer, while the second etch-stop layer with higher selectivity cushions against damage to the second dielectric layer, thereby preventing increased capacitance and RC delay that would otherwise result from misalignment damage.
3Reliability
If the etch-stop layer has high etch selectivity to the dielectric layer, then protection against misalignment damage is better, but the etching process becomes more difficult to control
Solution Approach 1:
The patent applies local quality by assigning different etch selectivity characteristics to different regions (etch-stop layers) within the same structure. The first etch-stop layer is designed with lower etch selectivity relative to the first dielectric layer for easier etching control in that region, while the second etch-stop layer is designed with higher etch selectivity relative to the second dielectric layer for better protection in that region. This spatial variation in etch selectivity allows the patent to simultaneously achieve good protection and manageable etching control.
Solution Approach 2:
The patent utilizes parameter changes by varying the etch selectivity parameter across different etch-stop layers. Instead of using a uniform etch selectivity throughout, the patent changes the selectivity parameter to create a gradient: the first etch-stop layer has lower selectivity (easier to etch through), while the second etch-stop layer has higher selectivity (better protection). This parameter variation enables the patent to balance protection effectiveness with etching process controllability.
Data Source
AI summary
The present disclosure relates to an integrated chip including a substrate. A first conductive wire is within a first dielectric layer that is over the substrate. A first etch-stop layer is over the first dielectric layer. A second etch-stop layer is over the first etch-stop layer. A conductive via is within a second dielectric layer that is over the second etch-stop layer. The conductive via extends through the second etch-stop layer and along the first etch-stop layer to the first conductive wire. A first lower surface of the second etch-stop layer is on a top surface of the first etch-stop layer. A second lower surface of the second etch-stop layer is on a top surface of the first conductive wire.