Dual-Feedback Level Shifter for 1.0 V to 3.3 V High-Speed Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional level shifting circuits face challenges in operating at speeds greater than 200 MHz, especially when shifting digital signals between 1.0 V and 3.3 V, as increasing device size leads to undesirable parasitic capacitance and using low threshold voltage devices complicates circuit design with additional protection requirements.
Innovation Solution
A level shifter design utilizing two positive feedback loops and high tolerance transistors with threshold voltages greater than 500 mV, eliminating the need for protection circuitry and allowing for compact layout, enabling operation at high frequencies with reduced distortions and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If device size is increased to generate higher switching current, then operating speed is improved, but parasitic capacitance increases
Solution Approach 1:
The patent changes the threshold voltage parameter of the transistors to be greater than 500mV (unconventional high threshold voltage), which allows the level shifter to operate at high speeds without requiring large device sizes, thereby avoiding increased parasitic capacitance
2Speed
If low threshold voltage devices are used to achieve higher operating speeds, then speed is improved, but circuit complexity increases due to protection circuitry requirements
Solution Approach 1:
The patent inverts the conventional approach by using high threshold voltage transistors (>500mV) instead of low threshold voltage devices. This inversion eliminates the need for protection circuitry while maintaining high operating speeds, thereby reducing circuit complexity
3Speed
If device size is increased to achieve higher operating speeds, then speed is improved, but area occupation increases
Solution Approach 1:
By changing the threshold voltage parameter to greater than 500mV, the patent enables high-speed operation with smaller device sizes, resulting in reduced area occupation for the level shifter circuit
Data Source
AI summary
A level shifter (10) includes a first transistor (12) having a gate configured to receive a first input signal, and a second transistor (14) having a gate configured to receive a second input signal. A first feedback circuit is connected to drains of the first transistor (12) and the second transistor (14). A second feedback circuit is connected to the first feedback circuit.