Dual-Feedback PLL for Accurate Beamforming Phase Control
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Solution Overview
Problem
Current phase locked loops (PLLs) in wireless systems face challenges in providing accurate phase shifts and programmable frequencies for beamforming systems, especially at high frequencies like 5G millimeter waves, while maintaining low phase noise and power efficiency, due to stringent phase noise requirements and the need for a large number of antenna elements.
Innovation Solution
A phase locked loop arrangement that includes a digital loop filter providing a digital control word to a digital controlled oscillator, with a frequency divider generating two feedback signals, one delayed, and comparator paths generating phase delay signals to adjust the oscillator signal, allowing for improved phase control accuracy and reduced hardware area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional PLL with single feedback path is used, then the circuit implementation is simple, but the phase control accuracy is insufficient for beamforming requirements
Solution Approach 1:
The feedback path is segmented into multiple paths (first feedback path and second feedback path), each with its own phase comparator. This segmentation allows independent phase measurement and control for different signal components, thereby improving phase control accuracy while managing circuit complexity through modular design
Solution Approach 2:
A delay element is introduced as an intermediary component in the second feedback path. This delay element enables the system to compare phases at different time instances, providing more comprehensive phase information for accurate beamforming control without requiring direct modification of the core PLL structure
2Adaptability or versatility
If multiple antenna elements for beamforming are implemented, then the system range and capacity increase, but the chip area and power consumption increase
Solution Approach 1:
The PLL circuit is designed with universal phase control capabilities that can serve multiple antenna elements. The multiple feedback paths and phase comparators create a reusable architectural pattern that can be instantiated for different beamforming configurations, reducing overall chip area compared to implementing separate PLLs for each antenna element
Solution Approach 2:
The system achieves beamforming adaptability by changing phase parameters through the feedback paths rather than requiring physical reconfiguration of antenna connections. This parameter-based control allows dynamic beam steering with minimal hardware changes, optimizing the balance between beamforming versatility and chip area
3Adaptability or versatility
If the oscillator frequency is made programmable for different frequency channels, then the system versatility improves, but the phase noise performance deteriorates
Solution Approach 1:
Multiple feedback paths with phase comparators provide enhanced feedback control that actively compensates for phase noise introduced by frequency programming. The system continuously monitors and corrects phase deviations, maintaining reliable phase noise performance across different frequency channels while preserving frequency programmability
Solution Approach 2:
The phase comparators and feedback paths are configured to anticipate and pre-compensate for phase noise effects before they degrade signal quality. By establishing robust phase control mechanisms in advance, the system maintains reliable performance when switching between frequency channels
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter (1) to provide a digital control word (DFC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), the second feedback signal (FBD) delayed with respect to the first feedback signal (FB); a first comparator path (4) configured to receive the first feedback signal (FB) and a second comparator path (5) configured to receive the second feedback signal (FBD), each of the first and second comparator path (4, 5) configured to provide a respective phase delaysignal (CS1, CS2) to the digital loop filter (1)in response to a respective adjustment signal (FA1, FA2) and a phase deviation between a common reference signal (FR) and the respective feedbacksignal (FB, FBD).