M-ary PAM Digital Equalizer with Dual Feedforward Architecture

Solution Overview

Problem

Conventional M-ary PAM systems face increased device area, power consumption, and circuit complexity due to the use of digital loop-unrolled decision-feedback equalizers, and alternative techniques like look-ahead loop-unrolled architectures complicate circuit design.

Innovation Solution

The implementation of multiple feedforward equalizers in combination with an improved look-ahead loop-unrolled N-tap decision-feedback equalizer in a receiver architecture, where one FFE operates as a primary equalizer and another as a secondary FFE to eliminate unnecessary decisions, reducing circuit complexity and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If digital loop-unrolled decision-feedback equalizer is used in M-ary PAM systems, then signal equalization performance is improved, but device area and power consumption increase

Engineering Contradiction:

Improvesignal equalization performanceVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The equalization function is segmented into two independent feedforward equalizers (FFE1 and FFE2) instead of using a single complex decision-feedback equalizer. Each FFE processes signals independently without requiring feedback paths, thereby reducing the overall circuit complexity and device area while maintaining equalization performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The feedback mechanism is extracted and removed from the system. Instead of using a decision-feedback equalizer that requires complex feedback loops and decision logic, the patent extracts only the feedforward equalization function, simplifying the circuit architecture and reducing power consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If digital loop-unrolled decision-feedback equalizer is used in M-ary PAM systems, then signal equalization performance is improved, but power consumption increases

Engineering Contradiction:

Improvesignal equalization performanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The equalization function is segmented into two independent feedforward equalizers (FFE1 and FFE2) instead of using a single complex decision-feedback equalizer. Each FFE processes signals independently without requiring feedback paths, thereby reducing the overall circuit complexity and device area while maintaining equalization performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The feedback mechanism is extracted and removed from the system. Instead of using a decision-feedback equalizer that requires complex feedback loops and decision logic, the patent extracts only the feedforward equalization function, simplifying the circuit architecture and reducing power consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

3Loss of time

If look-ahead loop-unrolled architecture is used, then timing requirements are relaxed, but circuit complexity increases

Engineering Contradiction:

Improvetiming requirementVSAvoidcircuit complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The equalization function is segmented into two independent feedforward equalizers (FFE1 and FFE2) instead of using a single complex decision-feedback equalizer. Each FFE processes signals independently without requiring feedback paths, thereby reducing the overall circuit complexity and device area while maintaining equalization performance.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10263663B2M-ary pulse amplitude modulation digital equalizer

Publication Date: 2019.04.16 INTEL CORP

AI summary

Some embodiments include apparatus and methods using an input node, an analog to digital converter (ADC) including an input coupled to the input node, a first feedforward equalizer (FFE) including an input coupled to an output of the ADC, a second FFE including an input coupled to the output of the ADC, and a decision feedback equalizer (DFE) including a first input, a second input, and an output, the first input coupled to an output of the first FFE, and the second input coupled to an output of the second FFE.