Dual FET Common-Electrode Structure for Gaussian I-V Control
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Solution Overview
Problem
Current CMOS technologies, such as FDSOI transistors, are limited in their ability to generate specific current-voltage characteristics like Gaussian shapes, which are essential for advanced applications in memory and machine learning, and lack the flexibility to perform functions that existing devices cannot handle.
Innovation Solution
A microelectronic device comprising two field effect transistors with a common electrode formed by doped zones, along with a dielectric layer and a rear gate, allowing for precise control of voltages applied to multiple gate electrodes, enabling the generation of Gaussian-type current-voltage characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional FDSOI transistor structures are used, then device simplicity and ease of manufacture are maintained, but the ability to generate Gaussian current-voltage characteristics and provide additional functionalities is lost
Solution Approach 1:
The patent combines two FDSOI transistors into a single integrated device structure where they share common elements (substrate, dielectric layers, and electrodes). This merging approach enables the generation of Gaussian current-voltage characteristics and provides additional functionalities (memory, logic gates) while minimizing the increase in device complexity through shared structural components.
Solution Approach 2:
The dual-transistor device is designed to perform multiple functions: it can generate Gaussian current-voltage characteristics for memory applications, implement logic gate operations (AND, OR, NOT), and operate as a conventional transistor when needed. The back gate and dual grid voltage control enable the same physical structure to serve different computational purposes.
2Ease of operation
If additional control points (back gate, dual grids) are introduced, then precise control over electrical behavior and new functionalities are achieved, but device complexity increases
Solution Approach 1:
The control of the device is segmented into multiple independent control points: a back gate for controlling the common electrode and front gates (first and second grids) for controlling individual transistor channels. This segmentation allows precise independent control of different aspects of device operation, enabling complex functionalities while maintaining clear control mechanisms for each function.
Solution Approach 2:
The back gate serves as an intermediary control element that modulates the common electrode potential, which in turn affects both transistors simultaneously. This intermediary approach allows a single control voltage to coordinate the operation of two transistors, achieving precise control over the combined device behavior without requiring direct control of each transistor individually.
3Adaptability or versatility
If two FDSOI transistors with common electrode are integrated, then Gaussian current-voltage characteristics and memory functionality are enabled, but manufacturing complexity increases
Solution Approach 1:
The patent merges two FDSOI transistor fabrication processes into a unified manufacturing approach where common structures (substrate preparation, dielectric layer deposition, electrode formation) are performed once for both transistors. This reduces the overall manufacturing complexity compared to fabricating two separate devices, while still enabling Gaussian characteristics and memory functionality through the integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for enhanced control over the device's electrical behavior, enabling the generation of Gaussian-type characteristics not achievable with conventional FDSOI transistors, providing additional functionalities and expanded application possibilities, including memory and machine learning applications.
Implementation Method 1
a back gate in contact with a bottom face of the dielectric layer
Implementation Method 2
a first gate dielectric, a second gate dielectric
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
The invention relates to a microelectronic device (1) comprising a first transistor (100) having a first drain and a first source, a first doped region (110) constituting one of the first drain and the first source, a second doped region (120) constituting the other of the first drain and the first source, a second transistor (200) having a second drain and a second source, a third doped region (210) constituting the second source or the second drain, a fourth doped region (220) constituting the other of the second drain and the second source, a dielectric layer (300) having an upper face (301) in contact with the four doped regions and a rear gate (400) in contact with a lower face (302) of the dielectric layer. The second doped region and the fourth doped region form a common electrode (1000).