Dual FIFO Synchronization for Semiconductor Data Transfer Noise
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Solution Overview
Problem
In semiconductor devices, the asynchrony between data transfer and clock signals for external reading leads to inefficiencies in high-speed data handling, particularly due to the distance and resistance in interconnect lines, which increases noise and jitter in data transfer.
Innovation Solution
The implementation of a first FIFO to synchronize data output from a memory circuit with a clock signal, followed by a second FIFO disposed near the input/output pads to further synchronize the data, reducing asynchrony and noise by minimizing the distance and resistance in interconnect lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred through long interconnect lines from memory circuit to input/output circuits, then data transfer capability is achieved, but noise and jitter increase due to resistance and distance
Solution Approach 1:
The patent divides the data transfer path into multiple segments by inserting FIFO circuits at strategic locations between the memory circuit and input/output circuits. This segmentation allows for synchronization points that break up the long interconnect line into manageable sections, reducing the cumulative effect of resistance and noise while maintaining overall data transfer capability.
Solution Approach 2:
The FIFO circuits act as intermediary elements between the memory circuit and input/output circuits. These intermediaries provide synchronization functionality that isolates the data transfer path from clock signal variations, thereby reducing noise and jitter propagation while enabling continued high-speed data transfer.
2Stability of the object's composition
If FIFO circuits are placed equidistant from each input/output circuit, then synchronization is achieved, but interconnect line resistance and noise increase
Solution Approach 1:
The patent applies local quality by placing FIFO circuits with different characteristics at different locations. Specifically, first FIFOs are positioned closer to the memory circuit while second FIFOs are positioned closer to the input/output circuits. This non-uniform distribution optimizes the balance between synchronization requirements and minimization of interconnect line resistance effects in different regions of the device.
3Reliability
If multiple FIFO stages are used to reduce asynchrony, then data synchronization improves, but device complexity increases
Solution Approach 1:
The patent designs the FIFO circuits to perform multiple functions: they serve as both data buffers and synchronization points, and they handle both data transfer and clock domain crossing. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving improved data synchronization through multiple FIFO stages.
Data Source
AI summary
A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.